adc1215s125hn/c1 NXP Semiconductors, adc1215s125hn/c1 Datasheet - Page 30
adc1215s125hn/c1
Manufacturer Part Number
adc1215s125hn/c1
Description
Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps With Input Buffer; Cmos Or Lvds Ddr Digital Outputs
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1215S125HNC1.pdf
(39 pages)
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NXP Semiconductors
Table 19.
Table 20.
ADC1215S_SER_1
Preliminary data sheet
Bit
7
6 to 4
3 to 2
1 to 0
Bit
7 to 5
4
3
2
1
0
Symbol
SW_RST
RESERVED[2:0]
-
OP_MODE[1:0]
Symbol
-
SE_SEL
DIFF_SE
-
CLKDIV
DCS_EN
Reset and operating mode control register (address 0005h) bit description
Clock control register (address 0006h) bit description
Access
R/W
R/W
Access
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Value
0
1
000
00
00
01
10
11
Value
000
0
1
0
1
0
0
1
0
1
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Rev. 01 — 12 April 2010
Description
reset digital section
reserved
not used
operating mode
Description
not used
single-ended clock input pin select
differential/single ended clock input select
not used
clock input divide by 2
duty cycle stabilizer
no reset
performs a reset on SPI registers
normal (Power-up)
Power-down
Sleep
normal (Power-up)
CLKM
CLKP
fully differential
single-ended
disabled
enabled
disabled
enabled
ADC1215S series
© NXP B.V. 2010. All rights reserved.
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