adc12qs065civs National Semiconductor Corporation, adc12qs065civs Datasheet - Page 12

• Manufacturer Part Number: adc12qs065civs
• Description: Quad 12-bit 65 Msps A/d Converter With Lvds Serialized Outputs
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
Operating on a single +3.0V supply, the ADC12QS065 uses
a pipeline architecture and has error correction circuitry to
help ensure maximum performance. The differential analog
input signal is digitized to 12 bits. The user has the choice of
using an internal 1.0 Volt or 0.5 Volt stable reference, or
using an external reference. Any external reference is buff-
ered on-chip to ease the task of driving that pin.
Sampled data is transformed into high speed serial output
LVDS data streams. Clock and frame LVDS pairs aid in data
capture. The ADC12QS065’s six differential pairs transmit
data over backplanes or cable and also make PCB design
easier.
The output word rate is the same as the clock frequency,
which can be between 20 MSPS and 65 MSPS (typical) with
fully specified performance at 65 MSPS. The analog input for
all channels are acquired at the rising edge of the clock and
the digital data for a given sample is delayed by the pipeline
for 9 clock cycles.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12QS065:
2.0 ANALOG INPUTS
There is one reference input pin, V
select an internal reference, or to supply an external refer-
ence. The ADC12QS065 has four analog signal input pairs,
V
4+ and V
pair. There are two VREG pins for decoupling the internal
1.8V regulator.
2.1 Reference Pins
The ADC12QS065 is designed to operate with an internal
1.0V or 0.5V reference, or an external 1.0V reference, but
performs well with external reference voltages in the range
of 0.8V to 1.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12QS065. Increasing
the reference voltage (and the input signal swing) beyond
1.2V may degrade THD for a full-scale input, especially at
higher input frequencies.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects
of noise currents in the ground path.
The six Reference Bypass Pins (VREFT12, VREFB12,
VCOM12, VREFT34, VREFB34 and VCOM34) are made
available for bypass purposes. All these pins should each be
bypassed to ground with a 0.1 µF capacitor. A 10 µF capaci-
tor should be placed between the VREFT12 and VREFB12
pins and between the VREFT34 and VREFB34 pins, as
shown in Figure 4 . This configuration is necessary to avoid
reference oscillation, which could result in reduced SFDR
and/or SNR.
IN
2.7V ≤ V
V
20 MHz ≤ f
0.8V ≤ V
0.5V ≤ V
D
1+ and V
= V
A
IN
A
REF
CM
= V
4- . Each pair of pins forms a differential input
≤ 3.6V
IN
CLK
≤ 2.0V
DR
≤ 1.2V (for an external reference)
1-, V
≤ 65 MHz
IN
2+ and V
IN
2- , V
REF
IN
, which is used to
3+ and V
IN
3-, V
IN
12
Smaller capacitor values than those specified will allow
faster recovery from the power down mode, but may result in
degraded noise performance. DO NOT LOAD these pins.
Loading any of these pins may result in performance degra-
dation.
The nominal voltages for the reference bypass pins are as
follows:
User choice of an on-chip or external reference voltage is
provided. When INTREF (pin 57) is high, the V
lects the internal reference voltage. The internal 1.0 Volt
reference is in use when the the V
When the V
Volt reference is in use. When INTREF (pin 57) is low, a
voltage in the range of 0.8V to 1.2V is applied to the V
and that is used for the voltage reference. When an external
reference is used, the V
ground with a 0.1 µF capacitor close to the reference input
pin. There is no need to bypass the V
internal reference is used.
2.2 Signal Inputs
The ADC12QS065 has 4 input channels. They are labelled
V
4+ and V
Figure 2 shows the expected input signal range. Note that
the common mode input voltage, V
range of 0.5V to 2.0V with a typical value of 1.5V.
The peaks of the individual input signals should each never
exceed 2.6V to maintain THD and SINAD performance.
The ADC12QS065 performs best with a differential input
signal with each input centered around a common mode
voltage, V
log input pin should not exceed the value of the reference
voltage or the output data will be clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For complex waveforms, however,
angular errors will result in distortion.
For single frequency sine waves the full scale error in LSB
can be described as approximately
IN
VCOM = 1.5 V
VREFT = VCOM + V
VREFB = VCOM − V
1+ and V
FIGURE 2. Expected Input Signal Range
IN
CM
4− . The input signal, V
REF
IN
. The peak-to-peak voltage swing at each ana-
E
1− , V
FS
pin is connected to AGND, the internal 0.5
= 4096 ( 1 - sin (90˚ + dev))
V
IN
IN
2+ and V
= (V
REF
REF
REF
IN
/ 2
/ 2
+) – (V
pin should be bypassed to
IN
2− , V
REF
IN
, is defined as
IN
pin is connected to V
CM
20106811
−)
IN
, should be in the
REF
3+ and V
pin when the
REF
IN
3− , V
pin se-
REF
pin
A
IN
.