adc12qs065civs National Semiconductor Corporation, adc12qs065civs Datasheet - Page 3

• Manufacturer Part Number: adc12qs065civs
• Description: Quad 12-bit 65 Msps A/d Converter With Lvds Serialized Outputs
• Manufacturer: National Semiconductor Corporation

ANALOG I/O
DIGITAL I/O
Pin Descriptions
Pin No.
32,49
10
14
11
13
24
59
22
58
23
60
21
55
56
57
31
25
26
46
44
36
34
3
7
4
6
VREFB12
VREFB34
VREFT12
VREFT34
VCOM12
VCOM34
Symbol
INTREF
REFPD
VREG
V
V
V
V
CLKB
DO1+
DO2+
DO3+
DO4+
V
V
V
V
V
DEN
CLK
PD
IN
IN
IN
IN
IN
IN
IN
IN
REF
1+
2+
3+
4+
1-
2-
3-
4-
Differential analog input pins. With a 1.0V reference voltage the differential
full-scale input signal level is 2.0 V
common mode voltage, V
V
best performance.
This pin is the reference select pin and the external reference input, used in
conjunction with the INTREF pin.
If the INTREF pin is set to V
With V
internal 0.5V reference is selected.
If the INTREF pin is set to AGND, then this pin is the input for an external
reference. A voltage in the range of 0.8 to 1.2V may be applied to this pin. V
should be bypassed to AGND with a 1.0 µF capacitor when an external
reference is used.
Top ADC Reference. This pin has to be driven to 1.9V if REFPD is high.
If REFPD is low, bypass this pin with a 0.1 µF low ESR capacitor to AGND and
a 10 µF low ESR capacitor to VREFB.
This is an analog output which can be used as a common mode voltage for the
inputs. It should be bypassed to AGND with a minimum of a 1.0 µF low ESR
capacitor in parallel with a 0.1 µF capacitor. Pin 23 may also be used as a 1.5V
temperature stable reference voltage.
Bottom ADC Reference. This pin has to be driven to 0.9V if REFPD is high.
If REFPD is low, bypass this pin with a 0.1 µF low ESR capacitor to AGND and
a 10 µF low ESR capacitor to VREFT.
These are bypass pins for the internal 1.8V regulator. Each pin should be
bypassed to AGND with a 1.0 µF capacitor
This pin acts as either a Non-Inverting Differential Clock input or a CMOS clock
input. If CLKB is used as the Inverting Clock input, CLK will act as the
Non-Inverting Clock input. If CLKB is tied to AGND, CLK will act as a CMOS
clock input. ADC power consumption will increase by about 40mW if a
Differential Clock is used.
Inverting Differential Clock input. If tied to AGND, CLK acts as a CMOS clock
input.
Internal reference enable input. When this pin is high, two internal reference
choices are selectable through the V
reference must be applied to V
Serial Data Output Enable. TTL level input. A low, puts the LVDS outputs in
High-Impedance State.
Power Down pin that, when high, puts the converter into the Power Down mode.
With REFPD high, user must drive VREFT12, VREFT34 and VREFB12 &
VREFB34 externally. With REFPD low, VREFT12, VREFT34 and VREFB12 &
VREFB34 are driven internally.
+ Serial Data Output. Non-inverting LVDS differential output.
COM
for single-ended operation, but a differential input signal is required for
REF
= V
A
, the internal 1.0V reference is selected. With V
3
COM
A
. The negative input pins may be connected to
, this pin is used as an internal reference select.
REF
Description
P-P
(pin 24).
REF
with each input pin voltage centered on a
pin. When this pin is low, an external
REF
=AGND, the
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REF