adc12qs065civs National Semiconductor Corporation, adc12qs065civs Datasheet - Page 17

• Manufacturer Part Number: adc12qs065civs
• Description: Quad 12-bit 65 Msps A/d Converter With Lvds Serialized Outputs
• Manufacturer: National Semiconductor Corporation

Applications Information
ence input pin and ground should be connected to a very
clean point in the ground plane. Traces for the input chan-
nels should be routed away from each other as much as
possible, with Ground plane between channels, to help mini-
mize crosstalk.
7.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 6. The gates used in the clock tree must
be capable of operating at frequencies much higher than
those used if added jitter is to be prevented.
Best performance will be obtained with a differential input
drive, compared with a single-ended drive, as discussed in
Sections 1.3.1 and 1.3.2.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
8.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 47Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12QS065
with a device that is powered from supplies outside the
range of the ADC12QS065 supply. Such practice may lead
to conversion inaccuracies and even to device damage.
FIGURE 6. Isolating the ADC Clock from other Circuitry
with a Clock Tree
(Continued)
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Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
rent spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 15 pF/pin
will cause t
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12QS065, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
mance. A small series resistor at each amplifier output and a
capacitor at the analog inputs (as shown in Figure 4 and
Figure 5) will improve performance. The LMH6702 and the
LMH6628 have been successfully used to drive the analog
inputs of the ADC12QS065.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting con-
figuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the speci-
fied range. As mentioned in Section 1.2, V
the range of
Operating outside of these limits could lead to performance
degradation.
Inadequate network on Reference Bypass pins (V
V
Section 1.2, these pins should be bypassed with 0.1 µF
capacitors to ground at V
RC of 1.5 Ω and 1.0 µF between pins V
between V
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
RN
A, V
RM
RP
OD
A, V
B and V
to increase, making it difficult to properly latch
DR
RP
B, V
and DRGND. These large charging cur-
0.8V ≤ V
RN
RN
B for best performance.
RM
B and V
A and V
REF
≤ 1.2V
RM
RM
B). As mentioned in
B and with a series
RP
A and V
REF
o
should be in
out of phase
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RN
A and
RP
A,