adc12qs065civs National Semiconductor Corporation, adc12qs065civs Datasheet - Page 4

• Manufacturer Part Number: adc12qs065civs
• Description: Quad 12-bit 65 Msps A/d Converter With Lvds Serialized Outputs
• Manufacturer: National Semiconductor Corporation

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ANALOG POWER
DIGITAL POWER
Pin Descriptions
12,15,17,19,
29,52,62,64
1,16,18,20,
33,38,43,
Pin No.
2,5,8,9,
30, 51
61,63
27,54
28,53
48,50
47
45
37
35
41
42
39
40
OUTCLK+
OUTCLK-
FRAME+
FRAME-
Symbol
DRGND
(Continued)
AGND
DGND
DO1-
DO2-
DO3-
DO4-
V
V
V
DR
D
A
- Serial Data Output. Inverting LVDS differential output.
LVDS output, it’s rising edge corresponds to the first serial bit of the output
streams. FRAME clock frequency is the same as the CLK frequency.
LVDS output clock. The data is valid on an output transition. Successive data
bits are captured on both edges of this clock. OUTCLK frequency is 6X the CLK
frequency.
Positive analog supply pins. These pins should be connected to a quiet +3.0V
source and bypassed to AGND with 0.1 µF capacitors located near these power
pins, and with a 10 µF capacitor.
The ground return for the analog supply.
Positive digital supply pin. This pin should be connected to the same quiet +3.0V
source as is V
the power pin and with a 10 µF capacitor.
The ground return for the digital supply.
Positive driver supply pin for the ADC12QS065’s output drivers. This pin should
be connected to a voltage source of +2.5V to V
with a 0.1 µF capacitor. If the supply for this pin is different from the supply used
for V
never exceed the voltage on V
the supply pin.
The ground return for the ADC12QS065’s output drivers.
A
and V
D
, it should also be bypassed with a 10 µF capacitor. V
A
4
and be bypassed to DGND with a 0.1 µF capacitor located near
D
. All bypass capacitors should be located near
Description
D
and be bypassed to DR GND
DR
should