adv7390 Analog Devices, Inc., adv7390 Datasheet
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adv7390 Summary of contents
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... Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 10-Bit SD/HD Video Encoder ADV7390/ADV7391/ADV7392/ADV7393 NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Programmable features ...
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... MPU Port Description................................................................... Operation.............................................................................. 23 SPI Operation.............................................................................. 24 Register Map.................................................................................... 25 Register Programming............................................................... 25 Subaddress Register (SR7 to SR0) ............................................ 25 ADV7390/ADV7391 Input Configuration ................................. 41 Standard Definition.................................................................... 41 Enhanced Definition/High Definition .................................... 41 Enhanced Definition (At 54 MHz) .......................................... 41 ADV7392/ADV7393 Input Configuration ................................. 42 Standard Definition.................................................................... 42 Enhanced Definition/High Definition .................................... 43 Enhanced Definition (At 54 MHz) .......................................... 43 Output Configuration .................................................................... 44 Features ...
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... Appendix 5–SD Timing..................................................................72 Appendix 6–HD Timing ................................................................77 Appendix 7–Video Output Levels.................................................78 SD YPrPb Output Levels—SMPTE/EBU N10 ........................78 ED/HD YPrPb Output Levels ...................................................79 REVISION HISTORY 10/06—Revision 0: Initial Version ADV7390/ADV7391/ADV7392/ADV7393 SD/ED/HD RGB Output Levels................................................80 SD Output Plots ..........................................................................81 Appendix 8–Video Standards........................................................82 Appendix 9–Configuration Scripts...............................................84 Standard Definition ....................................................................84 Enhanced Definition ..................................................................90 High Definition ...
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... TV-Out functionality. Cable detection and DAC auto power-down features ensure that power consumption is kept to a minimum. The ADV7390/ADV7391 have an 8-bit video input port that supports SD video formats over a SDR interface and HD video formats over a DDR interface. The ADV7392/ADV7393 have a 16-bit video input port that can be configured in a variety of ways ...
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... Output Compliance Output Capacitance, C OUT 1 Analog Output Delay DAC Analog Output Skew 1 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition. ADV7390/ADV7391/ADV7392/ADV7393 Conditions = 2 3.465 2. 3. DD_IO Conditions 1 Min ...
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... ADV7390/ADV7391/ADV7392/ADV7393 DIGITAL INPUT/OUTPUT SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 5. Parameter Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance Output High Voltage, V ...
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... Component Outputs (2×) Component Outputs (4×) RESET CONTROL RESET Low Time standard definition enhanced definition (525p/625p high definition, SDR = single data rate, DDR = dual data rate. 2 Video Data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391. 3 Video Control: HSYNC and VSYNC . 4 Guaranteed by characterization. 5 Guaranteed by design. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 VIDEO PERFORMANCE SPECIFICATIONS Table 8. Parameter STATIC PERFORMANCE Resolution 1 Integral Nonlinearity (INL Differential Nonlinearity (DNL) STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase 3 Signal-to-Noise Ratio (SNR) ENHANCED DEFINITION (ED) MODE Luma Bandwidth Chroma Bandwidth HIGH DEFINITION (HD) MODE Luma Bandwidth ...
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... CLKIN CONTROL HSYNC INPUTS VSYNC Y0 PIXEL PORT Cb0 PIXEL PORT CONTROL OUTPUTS ADV7390/ADV7391/ADV7392/ADV7393 In addition, refer to Table 30 for the ADV7390/ADV7391 input configuration and Table 31 for the ADV7392/ADV7393 input configuration Cr0 Y1 Cb2 Figure 2. SD Input, 8-/10-Bit 4:2:2 YCrCb (Input Mode 000) ...
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... ADV7390/ADV7391/ADV7392/ADV7393 CLKIN CONTROL HSYNC INPUTS VSYNC Y0 PIXEL PORT Cb0 PIXEL PORT CONTROL OUTPUTS CLKIN CONTROL HSYNC INPUTS VSYNC PIXEL PORT PIXEL PORT PIXEL PORT CONTROL OUTPUTS CLKIN* CONTROL HSYNC INPUTS VSYNC PIXEL PORT CONTROL OUTPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. ...
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... Figure 8. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ), Input Mode 111 CLKIN PIXEL PORT 3FF CONTROL OUTPUTS Figure 9. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111 ADV7390/ADV7391/ADV7392/ADV7393 00 XY Cb0 Y0 Cr0 Cr0 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Y OUTPUT HSYNC VSYNC PIXEL PORT PIXEL PORT PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY ...
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... PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 13. HD-DDR, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram ADV7390/ADV7391/ADV7392/ADV7393 a a Rev Page ...
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... ADV7390/ADV7391/ADV7392/ADV7393 HSYNC VSYNC PIXEL PORT SDA SCL SPI_SS SPI_SS SCLK t 5 MOSI MISO Figure 14. SD Input Timing Diagram (Timing Mode Figure 15. MPU Port Timing Diagram (I ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ADV7390/ADV7391/ADV7392/ADV7393 THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA Rating soldered in a circuit board for surface-mount packages ...
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... P4 4 ADV7390 ADV7391 DGND 6 TOP VIEW P5 7 (Not to Scale Figure 17. ADV7390/ADV7391 Pin Configuration Table 12. Pin Function Descriptions Pin Number ADV7390/91 ADV7392/93 Mnemonic 31 15 P15 37 CLKIN 27 33 ...
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... DGND 32 40 GND_IO enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7390, setting the LSB to 0 sets the I In the ADV7391, setting the LSB to 0 sets the address to 0x54. Setting sets the I ADV7390/ADV7391/ADV7392/ADV7393 Input/ Output Description I External Loop Filter for the Internal PLL ...
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... ADV7390/ADV7391/ADV7392/ADV7393 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 19. ED 8× Oversampling, PrPb Filter (Linear) Response ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 – ...
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... Figure 26. HD 4× Oversampling, Y Filter Response (Focus on Pass Band) 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 27. SD NTSC, Luma Low-Pass Filter Response ADV7390/ADV7391/ADV7392/ADV7393 –10 –20 –30 –40 –50 –60 –70 111.0 129.5 148.0 –10 –20 –30 –40 –50 – ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 31. SD 16× Oversampling, Y Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 32. SD Luma SSAF Filter Response MHz ...
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... Figure 38. SD Chroma 3.0 MHz Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 39. SD Chroma 2.0 MHz Low-Pass Filter Response ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –20 –30 –40 –50 –60 – Figure 40. SD Chroma 1.3 MHz Low-Pass Filter Response 0 –10 –20 – ...
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... ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 43. SD Chroma CIF Low-Pass Filter Response Rev Page –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 44. SD Chroma QCIF Low-Pass Filter Response ...
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... A1 is controlled by setting the ALSB/ SPI_SS pin of the ADV739x to Logic 0 or Logic ADDRESS CONTROL SET UP BY ALSB/SPI_SS Figure 45. ADV7390/ADV7392 Slave Address = 0xD4 or 0xD6 ADDRESS CONTROL SET UP BY ALSB/SPI_SS Figure 46. ADV7391/ADV7393 Slave Address = 0x54 or 0x56 To control the various devices on the bus, use the following protocol ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SDA SCL START ADDR R/W ACK SUBADDRESS ACK WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT P = STOP BIT SPI OPERATION The ADV739x supports a 4-wire serial (SPI-compatible) bus connecting multiple peripherals. Two inputs, master out slave in (MOSI) and serial clock (SCLK), and one output, master in slave out (MISO), carry information between a master SPI peripheral on the bus and the ADV739x ...
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... DAC 3: Power on/off. DAC 2: Power on/off. DAC 1: Power on/off. Reserved. ADV7390/ADV7391/ADV7392/ADV7393 REGISTER PROGRAMMING Table 13 to Table 27 describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 14. Register 0x01 to Register 0x09 SR7 to SR0 Register Bit Description 0x01 Mode Select Reserved. Register DDR Clock Edge Alignment. Note: Only used for ED HD DDR modes. Reserved. Input Mode. Note: See Reg. 0x30, Bits[7:3] for ED/HD format selection. Reserved. 0x02 Mode Reserved ...
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... SD/ED Oversample Rate Select. Reserved. 0x10 Cable Detection DAC 1 Cable Detect. Read Only. DAC 2 Cable Detect. Read Only. Reserved. Unconnected DAC auto power-down. Reserved. 0x13 Pixel Port P[7:0] Readback (ADV7390/ADV7391). 1 Readback A P[15:8] Readback (ADV7392/ADV7393). 0x14 Pixel Port P[7:0] Readback (ADV7392/ADV7393). 1 Readback B 0x16 Control Port Reserved. 1 Readback VSYNC Readback ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 16. Register 0x30 SR7 to SR0 Register Bit Description 0x30 ED/HD Mode ED/HD Output Standard. Register 1 ED/HD Input Synchronization Format. ED/HD Input Mode. 1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6. Bit Number ...
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... ED/HD CGMS Enable. ED/HD CGMS CRC Enable. 0x33 ED/HD Mode ED/HD Cr/Cb Sequence. Register 4 Reserved. ED/HD Input Form Sinc Compensation Filter on DAC 1, DAC 2, DAC 3. Reserved. ED/HD Chroma SSAF Filter. Reserved. ED/HD Double Buffering. 1 Available on the ADV7392/ADV7393 (40-pin devices) only. ADV7390/ADV7391/ADV7392/ADV7393 Bit Number ...
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... Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit Applies to the ADV7390 and ADV7392 only. 3 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. ...
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... ED/HD Gamma Curve B (Point 80). 0x53 ED/HD Gamma B5 ED/HD Gamma Curve B (Point 96). 0x54 ED/HD Gamma B6 ED/HD Gamma Curve B (Point 128). 0x55 ED/HD Gamma B7 ED/HD Gamma Curve B (Point 160). 0x56 ED/HD Gamma B8 ED/HD Gamma Curve B (Point 192). 0x57 ED/HD Gamma B9 ED/HD Gamma Curve B (Point 224). ADV7390/ADV7391/ADV7392/ADV7393 Bit Number ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 21. Register 0x58 to Register 0x5D SR7 to SR0 Register 0x58 ED/HD Adaptive Filter Gain 1 0x59 ED/HD Adaptive Filter Gain 2 0x5A ED/HD Adaptive Filter Gain 3 0x5B ED/HD Adaptive Filter Threshold A 0x5C ED/HD Adaptive Filter Threshold B 0x5D ED/HD Adaptive Filter Threshold C Bit Description 7 ED/HD Adaptive Filter Gain 1, Value A. ED/HD Adaptive Filter Gain 1, 0 Value B ...
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... ED/HD CGMS Type B ED/HD CGMS Type B Register 13 Data Bits. 0x6C ED/HD CGMS Type B ED/HD CGMS Type B Register 14 Data Bits. 0x6D ED/HD CGMS Type B ED/HD CGMS Type B Register 15 Data Bits. 0x6E ED/HD CGMS Type B ED/HD CGMS Type B Register 16 Data Bits. ADV7390/ADV7391/ADV7392/ADV7393 Bit Number ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 23. Register 0x80 to Register 0x83 SR7 to SR0 Register Bit Description 0x80 SD Mode SD Standard. Register 1 SD Luma Filter. SD Chroma Filter. 0x82 SD Mode SD PrPb SSAF Filter. Register 2 SD DAC Output 1. Reserved. SD Pedestal. SD Square Pixel Mode. SD VCR FF/RW Sync. SD Pixel Data Valid. SD Active Video Edge Control ...
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... When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. 2 Available on the ADV7392/ADV7393 (40-pin devices) only. ADV7390/ADV7391/ADV7392/ADV7393 Bit Number 7 6 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 25. Register 0x88 to Register 0x89 SR7 to SR0 Register Bit Description 0x88 SD Mode Reserved. Register 7 SD Noninterlaced Mode. SD Double Buffering. SD Input Format. SD Digital Noise Reduction. SD Gamma Correction Enable. SD Gamma Correction Curve Select. 0x89 SD Mode SD Undershoot Limiter. Register 8 Reserved. SD Black Burst Output on DAC Luma. ...
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... SD Pedestal Register 0 Pedestal on Odd Fields. 0x96 SD Pedestal Register 1 Pedestal on Odd Fields. 0x97 SD Pedestal Register 2 Pedestal on Even Fields. 0x98 SD Pedestal Register 3 Pedestal on Even Fields subcarrier frequency registers default to NTSC subcarrier frequency values. ADV7390/ADV7391/ADV7392/ADV7393 Bit Number ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 27. Register 0x99 to Register 0xA5 SR7 to SR0 Register Bit Description 0x99 SD CGMS/WSS 0 SD CGMS Data. SD CGMS CRC. SD CGMS on Odd Fields. SD CGMS on Even Fields. SD WSS. 0x9A SD CGMS/WSS 1 SD CGMS/WSS Data. SD CGMS Data. 0x9B SD CGMS/WSS 2 SD CGMS/WSS Data. 0x9C SD Scale LSB LSBs for SD Y Scale Value. ...
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... SD Gamma Curve B (Point 160). 0xB8 SD Gamma B8 SD Gamma Curve B (Point 192). 0xB9 SD Gamma B9 SD Gamma Curve B (Point 224). 0xBA SD Brightness Detect SD Brightness Value. 0xBB Field Count Register Field Count. Reserved. Revision Code. ADV7390/ADV7391/ADV7392/ADV7393 Bit Number ...
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... MV Control Bits. 0xED Macrovision MV Control Bits. 0xEE Macrovision MV Control Bits. 0xEF Macrovision MV Control Bits. 0xF0 Macrovision MV Control Bits. 0xF1 Macrovision MV Control Bit. 1 Macrovision registers are only available on the ADV7390 and the ADV7392. Bit Number ...
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... ADV7390/ADV7391 INPUT CONFIGURATION The ADV7390/ADV7391 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7390/ADV7391 defaults to standard definition (SD) mode upon power-up. Table 30 provides an overview of all possible input configurations. Each input mode is described in detail in this section. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ADV7392/ADV7393 INPUT CONFIGURATION The ADV7392/ADV7393 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7392/ADV7393 defaults to standard definition (SD) mode upon power-up. Table 31 provides an overview of all possible input configurations. Each input mode is described in detail in this section. ...
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... NOTES 1. SUBADDRESS 0x01 [2:1] SHOULD BE SET THIS CASE. 2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2. Figure 56. ED/HD-DDR Input Sequence (EAV/SAV)—Option B ADV7390/ADV7391/ADV7392/ADV7393 ENHANCED DEFINITION (AT 54 MHz) Subaddress 0x01, Bits[6:4] = 111 ED YCrCb data can be input in an interleaved 4:2:2 format on an 8-/10-bit bus at a rate of 54 MHz. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT CONFIGURATION The ADV739x supports a number of different output configurations. Table 32 to Table 34 lists all possible output configurations. Table 32. SD Output Configurations RGB/YPrPb Output Select 1 (0x02, Bit RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7. ...
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... ED/HD nonstandard timing mode. The user must ensure that appropriate pixel data is applied to the encoder where the blanking level is expected at the output. Macrovision (ADV7390/ADV7392 only) and output oversampling are not available in ED/HD nonstandard timing mode. The PLL must be disabled (Subaddress 0x00, Bit ED/HD nonstandard timing mode ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ED/HD TIMING RESET Subaddress 0x34, Bit 0 An ED/HD timing reset is achieved by setting the ED/HD timing reset control bit (Subaddress 0x34, Bit this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting. ...
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... NTSC CHANGE 4 RESET ADV739x DDS. 5 REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 “INPUT CONFIGURATION” TABLES FOR PIXEL DATA PIN ASSIGNMENTS. Figure 64. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11) SD VCR FF/RW SYNC Subaddress 0x82, Bit 5 In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for non- standard input video, that is, in fast forward or rewind modes ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Programming the F SC The subcarrier frequency register value is divided into four F registers as shown in the previous example. The four subcarrier frequency registers must be updated sequentially, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The subcarrier frequency updates only after the last subcarrier frequency register byte has been received by the ADV739x ...
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... In addition to the chroma filters listed in Table 38, the ADV739x contains an SSAF filter specifically designed for the color difference component outputs, Pr and Pb. This filter has a cutoff frequency of ~2.7 MHz and a gain of – 3.8 MHz (see Figure 67). This filter can be controlled with Subaddress 0x82, Bit 0. ADV7390/ADV7391/ADV7392/ADV7393 –10 –20 Subaddress 0x80 – ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3 The ADV739x includes a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by default. It can be disabled using Subaddress 0x33, Bit 3. The benefit of the filter is illustrated in Figure 68 and Figure 69. ...
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... GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion might use different scale values. ADV7390/ADV7391/ADV7392/ADV7393 For example, SMPTE 293M uses the following conversion: The programmable CSC matrix is used for external ED/HD pixel data and is not functional when internal test patterns are enabled ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SD HUE ADJUST CONTROL Subaddress 0xA0 When enabled, the SD hue adjust control register (Subaddress 0xA0) is used to adjust the hue on the SD composite and chroma outputs. This feature can be enabled using Subaddress 0x87, Bit 2. Subaddress 0xA0 contains the bits required to vary the hue of ...
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... The overall gain of the signal is increased from the reference signal. ADV7390/ADV7391/ADV7392/ADV7393 In Case B of Figure 71, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. Gamma correction is performed on the luma data only. The user can choose one of two correction curves, Curve A or Curve B ...
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... FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka) ADV7390/ADV7391/ADV7392/ADV7393 The derivative of the incoming signal is compared to the three programmable threshold values: ED/HD Adaptive Filter Threshold A, Threshold B, and Threshold C (Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D). The recommended threshold range 235, although any value in the range 255 can be used ...
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... ADV7390/ADV7391/ADV7392/ADV7393 CH1 500mV REF A 500mV 4.00µs Figure 75. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The ED/HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in Table 46 were used to achieve the results shown in Figure 75 ...
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... There are two DNR modes available: DNR mode and DNR sharpness mode. ADV7390/ADV7391/ADV7392/ADV7393 In DNR mode, if the absolute value of the filter output is smaller than the threshold assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Coring Gain Border—Subaddress 0xA3, Bits[3:0] These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal ...
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... IRE:FLT 0.5 0 –2 ADV7390/ADV7391/ADV7392/ADV7393 At the start of active video, the first three pixels are multiplied by ⅛, ½, and ⅞, respectively. Approaching the end of active video, the last three pixels are multiplied by ⅞, ½, and ⅛, respectively. All other active video pixels pass through unprocessed ...
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... ADV7390/ADV7391/ADV7392/ADV7393 EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the HSYNC and VSYNC pins (see Table 48 also possible to output synchronization signals on the HSYNC and VSYNC pins (see Table 49 to Table 51). ...
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... DAC 1 and/or DAC 2 once per frame, and if they are unconnected, automatically powers down some or all of the DACs. Which DAC or DACs are powered down depends on the selected output configuration. ADV7390/ADV7391/ADV7392/ADV7393 For CVBS/YC output configurations, if DAC 1 is unconnected, only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and DAC 3 power down. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 PRINTED CIRCUIT BOARD LAYOUT AND DESIGN DAC CONFIGURATIONS The ADV739x contains three DACs. All three DACs can be configured to operate in full-drive mode. Full-drive mode is defined as 34.7 mA full-scale current into a 37.5 Ω load, R Full-drive is the recommended mode of operation for the DACs. Alternatively, all three DACs can be configured to operate in low drive mode. Low drive mode is defined as 4.33 mA full-scale current into a 300 Ω ...
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... FREQUENCY (MHz) Figure 91. Output Filter Plot for HD, 4× Oversampling ADV7390/ADV7391/ADV7392/ADV7393 0 PRINTED CIRCUIT BOARD (PCB) LAYOUT 24n The ADV739x is a highly integrated circuit containing both –30 21n precision analog and high speed digital circuitry. It has been – ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Power Supply Decoupling It is recommended that each power supply pin be decoupled with 10 nF and 0.1 μF ceramic capacitors. The and both V pins should be individually decoupled to DD_IO DD ground. The decoupling capacitors should be placed as close as possible to the ADV739x with the capacitor leads kept as short as possible to minimize lead inductance μ ...
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... EXT_LF 150nF 170Ω LOOP FILTER COMPONENTS SHOULD BE LOCATED CLOSE TO THE EXT_LF AGND PGND DGND PIN AND ON THE SAME SIDE OF THE PCB AS THE ADV739x. AGND PGND DGND ADV7390/ADV7391/ADV7392/ADV7393 V POWER 0.1µF 0.01µF DD_IO SUPPLY DECOUPLING GND_IO GND_IO PV POWER 0.1µF 0.01µF DD SUPPLY ...
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... ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 1–COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV739x supports copy generation management system (CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both ...
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... REF 70% ± 10% 0mV –300mV 4T 3.128µs ± 90ns ADV7390/ADV7391/ADV7392/ADV7393 REF C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 49.1µs ± 0.5µs 2.235µs ± 20ns Figure 93. Standard Definition CGMS Waveform REF BIT 1 BIT BIT C10 C11 C12 21.2µ ...
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... ADV7390/ADV7391/ADV7392/ADV7393 +700mV 70% ± 10% 0mV –300mV 4T 4.15µs ± 60ns +700mV 70% ± 10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. +700mV 70% ±10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. REF BIT 1 BIT BIT ...
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... RUN-IN SEQUENCE 11.0µs ADV7390/ADV7391/ADV7392/ADV7393 (see Figure 100). The latter portion of Line 23 (after 42.5 μs from the falling edge of HSYNC ) is available for the insertion of video. WSS data transmission on Line 23 can be enabled using Subaddress 0x99, Bit possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 3–SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV739x supports closed captioning conforming to the standard television synchronizing waveform for color transmission. When enabled, closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning can be enabled using Subaddress 0x83, Bits[6:5] ...
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... SC F value to be written is only accepted after the F SC complete. ADV7390/ADV7391/ADV7392/ADV7393 ED/HD TEST PATTERNS The ADV739x is able to generate ED/HD color bar, black bar, and hatch test patterns. The register settings in Table 57 are used to generate an ED 525p hatch test pattern. All other registers are set as normal/ default ...
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... ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 5–SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... HSYNC and FIELD are input on the HSYNC and VSYNC pins, respectively. DISPLAY 522 523 524 525 HSYNC FIELD DISPLAY 260 261 262 263 264 HSYNC FIELD ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANK ODD FIELD VERTICAL BLANK 318 313 314 315 316 317 EVEN FIELD Figure 104 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 DISPLAY 622 623 624 625 HSYNC FIELD EVEN FIELD DISPLAY 309 310 311 312 HSYNC FIELD ODD FIELD Mode 1—Master Option (Subaddress 0x8A = this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace ...
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... A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV739x automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are output on the HSYNC and VSYNC pins, respectively. HSYNC VSYNC PIXEL DATA Figure 111. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave) ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANK ...
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... ADV7390/ADV7391/ADV7392/ADV7393 HSYNC VSYNC PIXEL DATA Figure 112. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace ...
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... APPENDIX 6–HD TIMING FIELD 1 1124 1125 VSYNC HSYNC FIELD 2 561 562 VSYNC HSYNC ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 115. 1080i HSYNC and VSYNC Input Timing Rev Page ...
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... ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 7–VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 116. Y Levels—NTSC 700mV Figure 117. Pr Levels—NTSC 700mV Figure 118. Pb Levels—NTSC 700mV 300mV Figure 119. Y Levels—PAL 700mV Figure 120. Pr Levels—PAL 700mV Figure 121. Pb Levels— ...
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... Figure 122. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 64 Figure 123. EIA-770.1 Standard Output Signals (525p/625p) ADV7390/ADV7391/ADV7392/ADV7393 INPUT CODE OUTPUT VOLTAGE 700mV 300mV OUTPUT VOLTAGE 700mV Figure 124. EIA-770.3 Standard Output Signals (1080i/720p) INPUT CODE OUTPUT VOLTAGE ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 126. SD/ED RGB Output Levels—RGB Sync Disabled R 700mV/525mV 300mV 0mV G 700mV/525mV 300mV 0mV B 700mV/525mV 300mV 0mV Figure 127. SD/ED RGB Output Levels—RGB Sync Enabled R 700mV/525mV 300mV ...
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... MICROSECONDS NOISE REDUCTION: 15.05dB PRECISION MODE OFF APL NEEDS SYNC SOURCE. 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = B SLOW CLAMP TO 0.00 AT 6.72µs FRAMES SELECTED 1, 2 Figure 132. NTSC Chroma ADV7390/ADV7391/ADV7392/ADV7393 VOLTS 0.6 0.4 0.2 0 –0 NOISE REDUCTION: 0.00dB APL = 39.1% 625 LINE NTSC SLOW CLAMP TO 0.00 AT 6.72µs VOLTS 0 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 8–VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 SAV/EAV: LINE 1–20; 561–583; 1124–1125 SAV/EAV: LINE 21–560; 584–1123 ...
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... Figure 139. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL 1 2 747 748 749 750 VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANK Figure 140. SMPTE 296M (720p ...
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... ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 9–CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by default. If required for a specific application, further features can be enabled. Table 58 lists the scripts available for SD modes of operation. Similarly, Table 89 and Table 106 list the scripts available for ED and HD modes of operation, respectively. ...
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... Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x8A 0x0C Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. ADV7390/ADV7391/ADV7392/ADV7393 Table 64. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 0x00 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 0x10 NTSC standard. SSAF luma filter enabled ...
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... PAL F value. SC 0x8D 0x8A PAL F value. SC 0x8E 0x09 PAL F value. SC 0x8F 0x2A PAL F value. SC ADV7390/ADV7391/ADV7392/ADV7393 Table 76. 8-Bit 625i YCrCb In, YPrPb Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 0x00 0x80 0x11 0x82 0xC1 0x8A 0x0C 0x8C 0xCB 0x8D 0x8A ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 79. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC1 Pixel data valid ...
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... PAL F value. SC 0x8D 0x8A PAL F value. SC 0x8E 0x09 PAL F value. SC 0x8F 0x2A PAL F value. SC ADV7390/ADV7391/ADV7392/ADV7393 Table 87. 16-Bit 625i RGB In, CVBS/Y-C Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 0x00 0x80 0x11 0x82 0xC3 0x87 0x80 0x88 0x08 0x8A 0x0C ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ENHANCED DEFINITION Table 89. ED Configuration Scripts Input Format Input Data Width 525p 8-Bit DDR 525p 8-Bit DDR 525p 10-Bit DDR 525p 10-Bit DDR 525p 16-Bit SDR 525p 16-Bit SDR 525p 16-Bit SDR 525p 16-Bit SDR 625p 8-Bit DDR 625p 8-Bit DDR ...
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... CLKIN. 0x30 0x04 525p @ 59.94 Hz. EAV/SAV synchro- nization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. ADV7390/ADV7391/ADV7392/ADV7393 Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 0x20 0x02 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 104. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled ...
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... All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x30 0x6C 1080i @ 30 Hz/29.97 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. ADV7390/ADV7391/ADV7392/ADV7393 Table 112. 16-Bit 1080i YCrCb In, YPrPb Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 0x10 0x30 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 117. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled ...
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... OUTLINE DIMENSIONS 5.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 6.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ADV7390/ADV7391/ADV7392/ADV7393 0.60 MAX 0.60 MAX 25 24 0.50 BSC EXPOSED 4.75 BSC SQ (BOTTOM VIEW) 0.50 0. 0.30 0.80 MAX 3.50 REF 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.23 0.08 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 142. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ × ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] No 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] No 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] N/A ADV739x Evaluation Platform Front-End Board. Yes ADV7390 Evaluation Board No ADV7391 Evaluation Board Yes ADV7392 Evaluation Board No ADV7393 Evaluation Board 2 C Standard Specification as defined by Philips. ...