adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 26

• Manufacturer Part Number: adv7390
• Description: Low Power, Chip Scale 10-bit Sd/hd Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7390/ADV7391/ADV7392/ADV7393
Table 14. Register 0x01 to Register 0x09
SR7 to
SR0
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
1
2
3
ED = enhanced definition = 525p and 625p.
Available on the ADV7392/ADV7393 (40-pin devices) only.
Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
Register
Mode Select
Register
Mode
Register 0
ED/HD CSC
Matrix 0
ED/HD CSC
Matrix 1
ED/HD CSC
Matrix 2
ED/HD CSC
Matrix 3
ED/HD CSC
Matrix 4
ED/HD CSC
Matrix 5
ED/HD CSC
Matrix 6
Bit Description
Reserved.
DDR Clock Edge Alignment.
Note: Only used for ED
HD DDR modes.
Reserved.
Input Mode.
Note: See Reg. 0x30, Bits[7:3]
for ED/HD format selection.
Reserved.
Reserved.
Test Pattern Black Bar.
Manual RGB Matrix Adjust.
Sync on RGB.
RGB/YPrPb Output Select.
SD Sync Output Enable.
ED/HD Sync Output Enable.
3
1
and
7
0
0
1
x
x
x
x
x
x
6
0
0
0
0
1
1
1
1
0
1
x
x
x
x
x
x
Rev. 0 | Page 26 of 96
5
0
0
1
1
0
0
1
1
0
1
x
x
x
x
x
x
Bit Number
4
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
3
0
0
1
x
x
x
x
x
x
2
0
0
1
1
0
1
x
x
x
x
x
x
x
x
x
x
x
1
0
1
0
1
0
x
x
0
0
0
x
x
x
x
x
x
x
Register Setting
Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
SD input.
ED/HD-SDR input
ED/HD-DDR input.
Reserved.
Reserved.
Reserved.
Reserved.
ED (at 54 MHz) input.
Zero must be written to these bits.
Disabled.
Enabled.
Disable manual RGB matrix adjust.
Enable manual RGB matrix adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
Output SD syncs on HSYNC and VSYNC pins.
No sync output.
Output ED/HD syncs on HSYNC and VSYNC
pins.
LSBs for GY.
LSBs for RV.
LSBs for BU.
LSBs for GV.
LSBs for GU.
Bits[9:2] for GY.
Bits[9:2] for GU.
Bits[9:2] for GV.
Bits[9:2] for BU.
Bits[9:2] for RV.
2
Reset
Value
0x00
0x20
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C