adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 72

• Manufacturer Part Number: adv7390
• Description: Low Power, Chip Scale 10-bit Sd/hd Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7390/ADV7391/ADV7392/ADV7393
APPENDIX 5–SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All
timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. If the VSYNC and HSYNC pins are not used, they should be tied high when using this mode.
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output on
HSYNC and the F bit is output on VSYNC .
H
F
H
F
260
522
DISPLAY
DISPLAY
NTSC/PAL M SYSTEM
523
261
(525 LINES/60Hz)
(625 LINES/50Hz)
INPUT PIXELS
PAL SYSTEM
524
262
ANALOG
VIDEO
525
263
264
1
Y
END OF ACTIVE
ODD FIELD
VIDEO LINE
C
r
Y
265
EVEN FIELD
2
F
F
4 CLOCK
4 CLOCK
EAV CODE
0
0
Figure 103. SD Timing Mode 0, Master Option, NTSC
266
EVEN FIELD
0
0
3
X
Y
Figure 102. SD Timing Mode 0, Slave Option
8
0
ODD FIELD
267
4
1
0
8
0
1
0
268
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5
VERTICAL BLANK
ANCILLARY DATA
0
0
269
VERTICAL BLANK
6
268 CLOCK
280 CLOCK
F
F
(HANC)
F
F
A
B
270
7
A
B
A
B
271
8
8
0
1
0
272
9
8
0
1
0
SAV CODE
4 CLOCK
F
F
4 CLOCK
273
10
START OF ACTIVE
0
0
VIDEO LINE
0
0
X
Y
274
11
C
b
Y C
1440 CLOCK
1440 CLOCK
r
Y
C
b
Y
283
20
C
r
Y
C
b
284
21
DISPLAY
285
DISPLAY
22