adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 16

• Manufacturer Part Number: adv7390
• Description: Low Power, Chip Scale 10-bit Sd/hd Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7390/ADV7391/ADV7392/ADV7393
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 12. Pin Function Descriptions
ADV7390/91
9 to 7, 4 to 2,
31, 30
13
27
26
25
24
23
22, 21, 20
12
11
10
14
19
5, 28
1
17
Pin Number
Figure 17. ADV7390/ADV7391 Pin Configuration
V
DGND
DD_IO
V
P2
P3
P4
DD
P5
P6
ADV7392/93
18 to 15, 11 to 8, 5
to 2, 39 to 37, 34
19
33
32
31
30
29
28, 27, 26
14
13
12
20
25
6, 35
1
23
1
2
3
4
5
6
7
8
(Not to Scale)
ADV7390/
ADV7391
PIN 1
INDICATOR
TOP VIEW
Mnemonic
P7 to P0
P15 to P0
CLKIN
HSYNC
VSYNC
SFL/MISO
R
COMP
DAC 1, DAC 2, DAC 3
SCL/MOSI
SDA/SCLK
ALSB/SPI_SS
RESET
V
V
V
PV
SET
AA
DD
DD_IO
DD
24 R
23 COMP
22 DAC 1
21 DAC 2
20 DAC 3
19 V
18 AGND
17 PV
SET
AA
DD
Input/
Output
I
I
I
I/O
I/O
I/O
I
O
O
I
I/O
I
I
P
P
P
P
Rev. 0 | Page 16 of 96
Description
8-Bit Pixel Port (P7 to P0). P0 is the LSB. Refer to Table 30 for input
modes (ADV7390/ADV7391).
16-Bit Pixel Port (P15 to P0). P0 is the LSB. Refer to Table 31 for input
modes (ADV7392/ADV7393).
Pixel Clock Input for HD (74.25 MHz), ED
SD (27 MHz).
Horizontal Synchronization Signal. This pin can also be configured to
output an SD, ED, or HD horizontal synchronization signal. See the
External Horizontal and Vertical Synchronization Control section.
Vertical Synchronization Signal. This pin can also be configured to
output an SD, ED, or HD vertical synchronization signal. See the
External Horizontal and Vertical Synchronization Control section.
Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data
Output (MISO). The SFL input is used to drive the color subcarrier
DDS system, timing reset, or subcarrier reset.
Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For
full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor
must be connected from R
example, into a 300 Ω load), a 4.12 kΩ resistor must be connected
from R
Compensation Pin. Connect a 2.2 nF capacitor from COMP to V
DAC Outputs. Full-drive and low-drive capable DACs.
Multifunctional Pin: I
Multifunctional Pin: I
Multifunctional Pin: ALSB sets up the LSB
address/SPI slave select (SPI_SS).
Resets the on-chip timing generator and sets the ADV739x into its
default mode.
Analog Power Supply (3.3 V).
Digital Power Supply (1.8 V). For dual-supply configurations, V
be connected to other 1.8 V supplies through a ferrite bead or
suitable filtering.
Input/Output Digital Power Supply (3.3 V).
PLL Power Supply (1.8 V). For dual-supply configurations, PV
be connected to other 1.8 V supplies through a ferrite bead or
suitable filtering.
SET
to AGND.
V
DGND
Figure 18. ADV7392/ADV7393 Pin Configuration
DD_IO
V
P10
P4
P6
P7
P8
P9
P5
DD
10
2
2
C Clock Input/SPI Data Input.
C Data Input/Output. Also, SPI clock input.
1
2
3
4
5
6
7
8
9
SET
PIN 1
INDICATOR
to AGND. For low drive operation (for
(Not to Scale)
ADV7392/
ADV7393
TOP VIEW
1
2
(27 MHz or 54 MHz), or
of the MPU I
30 R
29 COMP
28 DAC 1
27 DAC 2
26 DAC 3
25 V
24 AGND
23 PV
22 EXT_LF
21 PGND
AA
SET
DD
2
C
DD
DD
AA
can
can
.