adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 90

• Manufacturer Part Number: adv7390
• Description: Low Power, Chip Scale 10-bit Sd/hd Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION
Table 89. ED Configuration Scripts
Input Format
525p
525p
525p
525p
525p
525p
525p
525p
625p
625p
625p
625p
625p
625p
625p
625p
Table 90. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 91. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 92. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Setting
0x02
0x1C
0x10
0x04
0x01
Setting
0x02
0x1C
0x10
0x00
0x01
Setting
0x02
0x1C
0x10
0x10
0x04
0x01
Input Data Width
8-Bit DDR
8-Bit DDR
10-Bit DDR
10-Bit DDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
8-Bit DDR
8-Bit DDR
10-Bit DDR
10-Bit DDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p @ 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p @ 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p @ 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Synchronization Format
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
Rev. 0 | Page 90 of 96
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
Table 93. 16-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 94. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 95. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Setting
0x02
0x1C
0x10
0x10
0x00
0x01
Setting
0x02
0x1C
0x10
0x1C
0x01
Setting
0x02
0x1C
0x10
0x18
0x01
Output Color Space
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
RGB
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p @ 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p @ 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Table Number
Table 98
Table 100
Table 99
Table 101
Table 90
Table 91
Table 92
Table 93
Table 102
Table 104
Table 103
Table 105
Table 94
Table 95
Table 96
Table 97