adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 30

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adv7390

Manufacturer Part Number
adv7390
Description
Low Power, Chip Scale 10-bit Sd/hd Video Encoder
Manufacturer
Analog Devices, Inc.
Datasheet

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ADV7390/ADV7391/ADV7392/ADV7393
Table 18. Register 0x34 to Register 0x38
SR7 to
SR0
0x34
0x35
0x36
0x37
0x38
1
2
3
4
Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
Applies to the ADV7390 and ADV7392 only.
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Register
ED/HD Mode
Register 5
ED/HD Mode
Register 6
ED/HD Y Level
ED/HD Cr Level
ED/HD Cb Level
4
4
4
Bit Description
ED/HD Timing Reset.
ED/HD HSYNC Control.
ED/HD VSYNC Control.
Reserved.
ED Macrovision Enable.
Reserved.
ED/HD VSYNC Input/Field
Input.
ED/HD Horizontal/Vertical
Counter Mode.
Reserved.
Reserved.
ED/HD Sync on PrPb.
ED/HD Color DAC Swap.
ED/HD Gamma Correction
Curve Select.
ED/HD Gamma
Correction Enable.
ED/HD Adaptive
Filter Mode.
ED/HD Adaptive
Filter Enable.
ED/HD Test Pattern Y Level.
ED/HD Test Pattern Cr Level.
ED/HD Test Pattern Cb Level.
3
1
1
2
7
0
1
0
1
x
x
x
Rev. 0 | Page 30 of 96
6
0
1
0
1
x
x
x
5
0
0
1
x
x
x
Bit Number
4
0
1
0
1
x
x
x
3
1
0
1
x
x
x
2
0
1
0
1
x
x
x
1
0
1
0
x
x
x
0
0
1
0
x
x
x
Register Setting
Internal ED/HD timing counters enabled
Resets the internal ED/HD timing counters
ED Macrovision disabled
ED Macrovision enabled
Field/line counter free running
Disabled
Enabled
Cr level value
Cb level value
HSYNC output control (refer to
VSYNC output control (refer to
0 must be written to this bit
0 = Field input
1 = VSYNC input
Update field/line counter
Disabled
Enabled
DAC 2 = Pb, DAC 3 = Pr
DAC 2 = Pr, DAC 3 = Pb
Gamma Correction Curve A
Gamma Correction Curve B
Mode A
Mode B
Disabled
Enabled
Y level value
Table 51
Table 50
)
)
Reset
Value
0x48
0x00
0xA0
0x80
0x80

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