adv7344 Analog Devices, Inc., adv7344 Datasheet

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... DAC 4 14-BIT DAC 5 4× FILTER 14-BIT DAC 6 REFERENCE 16x/4x OVERSAMPLING AND CABLE DAC PLL DETECT PGND EXT_LF V COMP (2) DD REF ©2006 Analog Devices, Inc. All rights reserved. ® DACs ADV7344 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 R (2) SET www.analog.com ...

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... ADV7344 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Detailed Features .............................................................................. 4 General Description ......................................................................... 4 Specifications..................................................................................... 5 Power Supply and Voltage Specifications.................................. 5 Voltage Reference Specifications ................................................ 5 Input Clock Specifications .......................................................... 5 Analog Output Specifications..................................................... 6 Digital Input/Output Specifications........................................... 6 Digital Timing Specifications ..................................................... 7 MPU Port Timing Specifications ............................................... 8 Power Specifications .................................................................... 8 Video Performance Specifications ...

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... ED/HD Test Patterns ..................................................................74 Appendix 5—SD Timing................................................................75 Appendix 6—HD Timing ..............................................................80 Appendix 7—Video Output Levels...............................................81 REVISION HISTORY 10/06—Revision 0: Initial Version SD YPrPb Output Levels—SMPTE/EBU N10........................81 ED/HD YPrPb Output Levels ...................................................82 SD/ED/HD RGB Output Levels................................................83 SD Output Plots ..........................................................................84 Appendix 8—Video Standards ......................................................85 Outline Dimensions........................................................................87 Ordering Guide ...........................................................................87 Rev Page ADV7344 ...

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... The ADV7344 has a 30-bit pixel input port that can be configured in a variety of ways. SD video formats are supported over a SDR interface and ED/HD video formats are supported over SDR and DDR interfaces ...

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... SD = standard definition enhanced definition (525p/625p high definition. Conditions Conditions . REF = 2 3.465 2. 3. DD_IO Conditions 1 Min Typ SD/ (at 54 MHz 74. 74. Rev Page ADV7344 Min Typ Max 1.71 1.8 1.89 2.97 3.3 3.63 1.71 1.8 1.89 2.6 3.3 3.465 0.002 Min Typ Max 1.186 1.248 1.31 1.15 1.235 1.31 ±10 Max Unit MHz ...

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... ADV7344 ANALOG OUTPUT SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 5. Parameter 1 Full Drive Output Current (Full-Scale) 2 Low Drive Output Current (Full-Scale) DAC-to-DAC Matching Output Compliance Output Capacitance, C ...

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... SD ED/HD-SDR or ED/HD-DDR ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) SD ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) SD oversampling disabled SD oversampling enabled SD oversampling disabled SD oversampling enabled ED oversampling disabled ED oversampling enabled HD oversampling disabled HD oversampling enabled Rev Page ADV7344 Min Typ Max Unit 2.1 ns 2.3 ns 2.3 ns 1.7 ns 1 ...

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... ADV7344 MPU PORT TIMING SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 8. Parameter 2 1 MPU PORT MODE SCL Frequency SCL High Pulse Width SCL Low Pulse Width Hold Time (Start Condition), t ...

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... SET1 4.12 kΩ 300 Ω SET2 510 Ω 37.5 Ω SET1 4.12 kΩ 300 Ω SET2 L2 NTSC NTSC Luma ramp Flat field full bandwidth Rev Page ADV7344 Min Typ Max Unit 14 Bits 3 LSBs 4 LSBs 1 LSBs 3.2 LSBs 1.7 LSBs 1.4 LSBs 0.2 ±% 0.2 % ...

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... CONTROL OUTPUTS Figure 4. SD Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000 Data hold time Control output access time Control output hold time 14 In addition, refer to Table 31 for the ADV7344 input configuration Cr0 Cb2 t ...

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... Figure 7. ED/HD-SDR Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001) Rev Page Cb2 Cr2 Cb4 Cr4 Cb2 Cb3 Cb4 Cb5 Cr2 Cr3 Cr4 Cr5 ADV7344 ...

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... ADV7344 CONTROL INPUTS Y9 TO Y2/ *LUMA/CHROMACLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 8. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Pixel Input Mode (Input Mode 010 Y2/ CONTROL *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 9. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010) ...

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... CONTROL OUTPUTS Figure 13. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111) ED/HD INPUT Y1 Cb2 Y2 Cr2 Cr0 Y1 Cb2 Y2 Cr2 Cr0 Y1 Cb2 Cb0 Rev Page ADV7344 SD INPUT Cr2 Cr0 Y1 ...

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... ADV7344 Y OUTPUT P_HSYNC P_VSYNC P_BLANK Y9 TO Y2/ C2/ AND b AS PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY ...

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... SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 17. HD-DDR, 8-/10-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram b b Rev Page ADV7344 Cb0 Cr0 ...

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... ADV7344 S_HSYNC S_VSYNC S9 TO S0/Y9 TO Y0* *SELECTED BY SUBADDRESS 0x01, BIT 7. SDA SCL SPI_SS SCLK t 5 MOSI MISO Figure 18. SD Input Timing Diagram (Timing Mode Figure 19. MPU Port Timing Diagram (I ...

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... Values are based on a JEDEC 4-layer test board. −0 +0.3 V The ADV7344 is a Pb-free product. The lead finish is 100% pure −0 +0 electroplate. The device is RoHS compliant, suitable for Pb- −0 +0.3 V free applications up to 255°C (±5°C) IR reflow (JEDEC STD-20). ...

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... R I SET2 45, 35 COMP1, O COMP2 PIN ADV7344 7 TOP VIEW 8 (Not to Scale Figure 21. Pin Configuration Description 10-Bit Pixel Port ( the LSB. Refer to Table 31 for input modes. ...

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... GND_IO enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7344, setting the LSB to 0 sets the I Description DAC Outputs. Full and low drive capable DACs. DAC Outputs. Low drive only capable DACs. 2 Multifunctional Pin Clock Input/SPI Data Input. ...

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... ADV7344 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 22. ED 8× Oversampling, PrPb Filter (Linear) Response ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 – ...

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... Rev Page FREQUENCY (MHz) Figure 31. SD PAL, Luma Low-Pass Filter Response FREQUENCY (MHz) Figure 32. SD NTSC, Luma Notch Filter Response FREQUENCY (MHz) Figure 33. SD PAL, Luma Notch Filter Response ADV7344 ...

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... ADV7344 Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 34. SD, 16× Oversampling, Y Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 35. SD Luma SSAF Filter Response MHz ...

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... Figure 44. SD Chroma 1.0 MHz Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – Figure 45. SD Chroma 0.65 MHz Low-Pass Filter Response Rev Page ADV7344 FREQUENCY (MHz FREQUENCY (MHz FREQUENCY (MHz) ...

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... ADV7344 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 46. SD Chroma CIF Low-Pass Filter Response Rev Page –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 47. SD Chroma QCIF Low-Pass Filter Response ...

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... C-compatible) The ADV7344 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/ W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. ...

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... On the first SCLK rising edge after ALSB/ SPI_SS has been driven low, the read command, defined as 0xD5, is written, MSB first, to the ADV7344 over the MOSI line. Subsequently, 8-bit data bytes are read from the ADV7344, MSB first, on the MISO line. The data bytes are clocked out of the ADV7344 on the falling edge of SCLK ...

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... REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV7344 via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines which register the next read or write operation accesses. All communication through the MPU port starts with an access to the subaddress register. ...

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... ADV7344 Table 15. Register 0x01 to Register 0x09 SR7 to SR0 Register Bit Description 0x01 Mode Select Reserved. Register DDR Clock Edge Alignment. Note: Only used for ED HD DDR modes. Reserved. Input Mode. Note: See Reg. 0x30, Bits[7:3] for ED/HD format selection. Y/C/S Bus Swap. 0x02 Mode Reserved ...

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... Rev Page ADV7344 Reset 0 Register Setting Value 0 0% 0x00 1 +0.018% 0 +0.036% … … 1 +7.382% 0 +7.5% 0 −7.5% 1 −7.382% 0 −7.364% … … 1 −0.018 ...

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... ADV7344 Table 17. Register 0x12 to Register 0x17 SR7 to SR0 Register 0x12 Pixel Port Readback (S Bus MSBs) 0x13 Pixel Port Readback (Y Bus MSBs) 0x14 Pixel Port Readback (C Bus MSBs) 0x15 Pixel Port Readback (S, Y, and C Bus LSBs) 0x16 Control Port Readback 0x17 Software Reset ...

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... SMPTE 274M- SMPTE 274M-10, SMPTE 274M-11 ITU-R BT.709-5. 10011–11111 Reserved. Rev Page ADV7344 Reset Note Value ED 0x00 525p @ 59.94 Hz 525p @ 59.94 Hz 625p @ 50 Hz 625p @ 50 Hz 720p @ 60/59.94 Hz 720p @ 50 Hz 720p @ 30/29.97 Hz 720p @ 25 Hz 720p @ 24/23.98 Hz 1035i @ 60/59.94 Hz 1080i @ 30/29.97 Hz 1080i @ 25 Hz 1080p @ 0/29 ...

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... ADV7344 Table 19. Register 0x31 to Register 0x33 SR7 to SR0 Register Bit Description 0x31 ED/HD Mode ED/HD Pixel Data Valid. Register 2 Reserved. ED/HD Test Pattern Enable. ED/HD Test Pattern Hatch/Field. ED/HD VBI Open. ED Only Undershoot Limiter. ED/HD Sharpness Filter. 0x32 ED/HD Mode ED/HD Y Delay with Respect to Falling Register 3 Edge of HSYNC. ED/HD Color Delay with Respect to Falling Edge of HSYNC ...

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... Rev Page ADV7344 Register Setting Internal ED/HD timing counters enabled. Resets the internal ED/HD timing counters. HSYNC output control. VSYNC output control. P_BLANK active high. P_BLANK active low. Macrovision disabled. Macrovision enabled. 0 must be written to this bit field input. ...

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... ADV7344 Table 21. Register 0x36 to Register 0x43 SR7 to SR0 Register Bit Description 1 0x36 ED/HD Y Level ED/HD Test Pattern Y Level. 1 0x37 ED/HD Cr Level ED/HD Test Pattern Cr Level. 1 0x38 ED/HD Cb Level ED/HD Test Pattern Cb Level. 0x39 ED/HD Mode Reserved. Register 7 ED/HD EIA/CEA-861B Synchronization Compliance. Reserved. 0x40 ED/HD Sharpness ED/HD Sharpness Filter Gain, Filter Gain Value A ...

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... Gain … … … … Gain Gain B = −8 … … … … Gain B = − Threshold Threshold Threshold C ADV7344 Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 ...

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... ADV7344 Table 24. Register 0x5E to Register 0x6E SR7 to SR0 Register Bit Description 0x5E ED/HD CGMS Type B ED/HD CGMS Type B Register 0 Enable. ED/HD CGMS Type B CRC Enable. ED/HD CGMS Type B Header Bits. 0x5F ED/HD CGMS Type B ED/HD CGMS Type B Register 1 Data Bits. 0x60 ED/HD CGMS Type B ED/HD CGMS Type B Register 2 Data Bits. ...

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... Disabled. 1 Enabled Closed captioning disabled Closed captioning on odd field only Closed captioning on even field only Closed captioning on both fields. 0 Reserved. Rev Page ADV7344 Reset Value 0x10 0x0B Table 32 Output in the section. Table 32 Output in the section. 0x04 ...

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... ADV7344 Table 26. Register 0x84 to Register 0x89 SR7 to SR0 Register Bit Description 0x84 SD Mode SD VSYNC-3H. Register 4 SD SFL/SCR/TR Mode Select. SD Active Video Length. SD Chroma. SD Burst. SD Color Bars. SD Luma/Chroma Swap. 0x86 SD Mode NTSC Color Subcarrier Adjust (Delay Register 5 from the falling edge of output HSYNC pulse to start of color burst) ...

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... Disabled −11 IRE −6 IRE −1.5 IRE must be written to this bit. 0 Disabled. 1 Enabled Disabled clock cycles clock cycles Reserved must be written to these bits. Rev Page ADV7344 Reset Value 0x00 0x00 ...

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... ADV7344 Table 27. Register 0x8A to Register 0x98 SR7 to SR0 Register Bit Description 0x8A SD Timing Register 0 SD Slave/Master Mode. SD Timing Mode. Reserved. SD Luma Delay. SD Minimum Luma Value. SD Timing Reset. 0x8B SD Timing Register 1 SD HSYNC Width. (Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit 0 = 1.) SD HSYNC to VSYNC Delay ...

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... SD Hue Adjust Bits[7: Brightness Bits[6:0] Disabled Enabled −4 dB … … … … … … … … … … ADV7344 Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...

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... ADV7344 SR7 to SR0 Register Bit Description 0xA3 SD DNR 0 Coring Gain Border. Note: In DNR mode, the values in brackets apply. Coring Gain Data. Note: In DNR mode, the values in brackets apply. 0xA4 SD DNR 1 DNR Threshold. Border Area. Block Size Control. 0xA5 SD DNR 2 DNR Input Select. ...

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... Rev Page ADV7344 Register Reset Setting Value 0x00 0x00 0x00 0x00 ...

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... ADV7344 INPUT CONFIGURATION The ADV7344 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7344 defaults to standard definition only (SD only) upon power-up. Table 31 provides an overview of all possible input configurations. Each input mode is described in detail in the following sections. ...

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... S0, Y0, and C0 are the respective bus LSBs in 30-bit input mode. SIMULTANEOUS STANDARD DEFINITION AND ENHANCED DEFINITION/HIGH DEFINITION Subaddress 0x01, Bits[6:4] = 011 or 100 The ADV7344 is able to simultaneously process SD 4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz SD clock signal must be provided on the CLKIN_A pin. The ED/HD clock signal must be provided on the CLKIN_B pin. SD input synchronization signals are provided on the S_HSYNC and S_VSYNC pins ...

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... Y0 being the LSB in 10-bit input mode. CLKIN_A Y[9:0] 3FF 00 Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV) MPEG2 DECO DER 54MHz YCrCb YCrCb INTERLACED TO PROGRESSIVE Figure 58. ED Only (at 54 MHz) Example Application Rev Page Cb0 Y0 Cr0 Y1 CLKIN_A ADV7344 10 Y[9:0] P_VSYNC, 3 P_HSYNC, P_BLANK ...

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... OUTPUT CONFIGURATION The ADV7344 supports a number of different output configurations. Table 32 to Table 35 lists all possible output configurations. Table 32. SD Only Output Configurations RGB/YPrPb SD DAC SD DAC Output Select 1 Output 2 Output 1 (0x02, Bit 5) (0x82, Bit 2) (0x82, Bit ...

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... For any ED/HD input data that does not conform to the standards available in the ED/HD input mode table (Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing mode can be used to interface to the ADV7344. ED/HD nonstandard timing mode can be enabled by setting Subaddress 0x30, Bits[7:3] to 00001. Table 36. Output Oversampling Modes and Rates ...

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... Subaddress 0xBB can be used to identify the number of the active field. Subcarrier Frequency Lock (SFL) Mode In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7344 can be used to lock to an external video source. The SFL mode allows the ADV7344 to automatically alter the subcarrier frequency to compensate for line length variations ...

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... Mode 0. VERTICAL BLANKING INTERVAL Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4 The ADV7344 is able to accept input data that contains VBI data (such as CGMS, WSS, VITS) in SD, ED, and HD modes. If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress 0x83, Bit 4 for SD), VBI data is not present at the output and the entire VBI is blanked ...

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... PAL operation and Subaddress 0x88, Bit 1 should be set SQUARE PIXEL MODE Subaddress 0x82, Bit 4 The ADV7344 can be used to operate in square pixel mode (Subaddress 0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation ...

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... The desired response can be programmed using Subaddress 0xA2. The variation of frequency responses are shown in Figure 36 to Figure 38. In addition to the chroma filters listed in Table 39, the ADV7344 contains an SSAF filter specifically designed for the color difference component outputs, Pr and Pb. This filter has a cutoff frequency of ~2.7 MHz and a gain of – ...

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... Bit 7) YPrPb 1 0 RGB 0 0 YPrPb 1 1 RGB 0 1 YPrPb/RGB Out RGB In/YCrCb In Output (Reg. 0x02, Bit 5) (Reg. 0x35, Bit 1) YPrPb 1 0 RGB 0 0 RGB 0 1 ADV7344 Cb Value 128 (0x80) 128 (0x80) 90 (0x5A) 54 (0x36) 240 (0xF0) 16 (0x10) 166 (0xA6) 202 (0xCA) ...

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... ADV7344 If RGB output is selected, the ED/HD CSC matrix scalar uses the following equations × × × Y − × Pb) − × Pr × × Pb Note that subtractions are implemented in hardware. If YPrPb output is selected, the following equations are used × × ...

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... The ADV7344 provides a range of ±22.5° in increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits, respectively, of the attainable adjustment in NTSC mode ...

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... ADV7344 DOUBLE BUFFERING Subaddress 0x33, Bit 7 for ED/HD, Subaddress 0x88, Bit 2 for SD Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not made during active video, but take effect prior to the start of the active video on the next field. ...

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... The gamma curves in Figure 70 and Figure 71 are examples only; any user-defined curve in the range from 16 to 240 is acceptable. 300 250 200 150 100 50 200 250 0 0 Figure 71. Signal Input (Ramp) and Selectable Output Curves Rev Page ADV7344 γ ⎞ − ⎛ ⎞ ⎟ × − + ⎜ ⎟ ...

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... ADV7344 ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D There are three filter modes available on the ADV7344, a sharpness filter mode and two adaptive filter modes. ED/HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 72, the ED/HD sharpness filter must be enabled (Subaddress 0x31, Bit 7) and the ED/HD adaptive filter must be disabled (Subaddress 0x35, Bit 7) ...

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... Reference 0x02 0x30 0x31 0x35 0x40 0x58 a 0x59 b 0x5A c 0x5B d 0x5C e 0x5D f Rev Page 4.00µs CH1 ALL FIELDS 500mV 4.00µs 1 9.99978ms Register Setting 0xFC 0x38 0x20 0x00 0x81 0x80 0x00 0xAC 0x9A 0x88 0x28 0x3F 0x64 ADV7344 ...

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... ADV7344 Figure 74. Input Signal to ED/HD Adaptive Filter Figure 75. Output Signal from ED/HD Adaptive Filter (Mode A) When changing the adaptive filter mode to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 76 can be obtained. Figure 76. Output Signal from ED/HD Adaptive Filter (Mode B) SD DIGITAL NOISE REDUCTION Subaddress 0xA3 to Subaddress 0xA5 Digital noise reduction (DNR) is applied to the Y data only ...

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... PIXEL BLOCK same position regardless of variations in input timing of the data. Rev Page 1.0 FILTER D 0.8 FILTER C 0.6 0.4 FILTER B 0.2 FILTER FREQUENCY (MHz) Figure 80. SD DNR Input Select ADV7344 6 ...

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... ADV7344 SD ACTIVE VIDEO EDGE CONTROL Subaddress 0x82, Bit 7 The ADV7344 is able to control fast rising and falling signals at the start and end of active video in order to minimize ringing. When the active video edge control feature is enabled (Subaddress 0x82, Bit 7 = 1), the first three pixels and the last ...

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... EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For synchronization purposes, the ADV7344 is able to accept either time codes embedded in the input pixel data or external synchronization signals provided on the S_HSYNC , S_VSYNC , P_HSYNC , P_VSYNC , and P_BLANK pins (see Table 49 also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52). ...

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... For YPrPb and RGB output configurations, only DAC 1 is monitored, that is, the luma or green output is monitored. Once per frame, the ADV7344 monitors DAC 1 and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1, respectively cable is detected on one of the DACs, the relevant bit is set to 0. ...

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... Alternatively, the ADV7344 can be used with an external voltage reference by connecting the reference source to the V pin. For optimal performance, an external voltage reference such as the AD1580 should be used with the ADV7344 external voltage reference is not used, a 0.1 μF capacitor should be connected from the V pin to V ...

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... MAGNITUDE (dB) 16n 320 The external loop filter components and components connected 14n to the COMP, V 240 PHASE 12n possible to and on the same side of the PCB as the ADV7344. (Degrees) 160 Adding vias to the PCB to get the components closer to the 10n 80 ADV7344 is not recommended ...

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... The DAC output traces should be kept as short as possible. The termination resistors on the DAC output traces should be placed as close as possible to and on the same side of the PCB as the ADV7344. To avoid crosstalk between the DAC outputs recommended that as much space as possible be left between the traces connected to the DAC output pins ...

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... NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP AND DAC OUTPUT PINS SHOULD BE LOCATED SET REF CLOSE TO AND ON THE SAME SIDE OF THE PCB AS THE ADV7344 WHEN OPERATING MODE, THE I C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB/SPI_SS PIN: ...

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... CGMS data is inserted on Line 41. The 525p CGMS data registers are at Subaddress 0x41, Subaddress 0x42, and Subaddress 0x43. The ADV7344 also supports CGMS Type B packets in 525p mode in accordance with CEA-805-A. When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1), 525p CGMS Type B data is inserted on Line 40. The 525p CGMS Type B data registers are at Subaddress 0x5E to Subaddress 0x6E ...

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... ADV7344 +100 IRE +70 IRE 0 IRE –40 IRE 11.2µs +700mV 70% ± 10% 0mV –300mV 5.8µs ± 0.15µs 6T PEAK WHITE 500mV ± 25mV SYNC LEVEL 5.5µs ± 0.125µs +700mV 70% ± 10% 0mV –300mV 4T 3.128µs ± 90ns REF C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 2.235µ ...

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... Rev Page ADV7344 CRC SEQUENCE BIT 20 × 2200/77) = 1.038µs H CRC SEQUENCE P122 P123 P124 P125 P126 P127 CRC SEQUENCE BIT 134 . . P122 P123 P124 P125 P126 P127 BIT 134 ...

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... ADV7344 APPENDIX 2—SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV7344 supports wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long ...

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... The FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA-608 describe the closed captioning information for Line 21 and Line 284. The ADV7344 uses a single buffering method. This means that the closed captioning buffer is only 1-byte deep. Therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems ...

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... ADV7344 APPENDIX 4—INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV7344 is able to generate SD color bar and black bar test patterns. The register settings in Table 56 are used to generate an SD NTSC 75% color bar test pattern. CVBS output is available on DAC 4, S-Video (Y/C) output is on DAC 5 and DAC 6, and YPrPb output is on DAC 1 to DAC 3 ...

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... Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = The ADV7344 is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...

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... Mode 1—Slave Option (Subaddress 0x8A = this mode, the ADV7344 accepts horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. HSYNC and FIELD are input on the S_HSYNC and S_VSYNC pins, respectively ...

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... In this mode, the ADV7344 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the S_HSYNC and S_VSYNC pins, respectively ...

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... In this mode, the ADV7344 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are output on the S_HSYNC and S_VSYNC pins, respectively. ...

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... Mode 3—Master/Slave Option (Subaddress 0x8A = this mode, the ADV7344 accepts or generates horizontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. ...

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... ADV7344 APPENDIX 6—HD TIMING FIELD 1 1124 1125 P_VSYNC P_HSYNC FIELD 2 561 562 P_VSYNC P_HSYNC VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 113. 1080i HSYNC and VSYNC Input Timing Rev Page ...

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... SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 114. Y Levels—NTSC 700mV Figure 115. Pr Levels—NTSC 700mV Figure 116. Pb Levels—NTSC 700mV 300mV Figure 117. Y Levels—PAL 700mV Figure 118. Pr Levels—PAL 700mV Figure 119. Pb Levels—PAL Rev Page ADV7344 ...

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... ADV7344 ED/HD YPRPB OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 120. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 64 Figure 121. EIA-770.1 Standard Output Signals (525p/625p) INPUT CODE ...

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... Figure 125. SD/ED RGB Output Levels—RGB Sync Enabled R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 126. HD RGB Output Levels—RGB Sync Disabled R 700mV/525mV 600mV 300mV 0mV G 700mV/525mV 600mV 300mV 0mV B 700mV/525mV 600mV 300mV 0mV Figure 127. HD RGB Output Levels—RGB Sync Enabled Rev Page ADV7344 ...

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... ADV7344 SD OUTPUT PLOTS VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72µs FRAMES SELECTED 1, 2 Figure 128. NTSC Color Bars (75%) VOLTS IRE:FLT 0.6 0 –0.2 F2 L238 0 10 ...

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... SAV CODE ACTIVE LINE CLOCK 188 192 2111 DIGITAL SAV CODE ACTIVE LINE CLOCK 853 857 0 719 ACTIVE VIDEO ADV7344 ...

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... ADV7344 ACTIVE VIDEO 622 623 624 625 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 VERTICAL BLANK Figure 137. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL Figure 138. SMPTE 296M (720p) VERTICAL BLANKING INTERVAL ...

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... LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 140. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters 1 Macrovision Antitaping Package Description Yes 64-Lead Low Profile Quad Flat Package [LQFP] Yes Evaluation Platform Rev Page ADV7344 49 48 10.20 10. 0.27 0.22 0.17 Package Option ST-64-2 ...

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... ADV7344 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...