adv7344 Analog Devices, Inc., adv7344 Datasheet - Page 25

• Manufacturer Part Number: adv7344
• Description: Multiformat Video Encoder Six 14-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the
ADV7344 through one of the following protocols:
•
•
After power-up or reset, the MPU port is configured for I
operation. SPI operation can be invoked at any time by
following the procedure outlined in the SPI Operation section.
I
The ADV7344 supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. This port
operates in an open-drain configuration. Two inputs, serial data
(SDA) and serial clock (SCL), carry information between any
device connected to the bus and the ADV7344. Each slave
device is recognized by a unique address. The ADV7344 has
four possible slave addresses for both read and write operations.
These are unique addresses for each device and are illustrated in
Figure 48. The LSB either sets a read or write operation. Logic 1
corresponds to a read operation, while Logic 0 corresponds to a
write operation. A1 is controlled by setting the ALSB/ SPI_SS
pin of the ADV7344 to Logic 0 or Logic 1.
To control the various devices on the bus, use the following
protocol. The master initiates a data transfer by establishing a
start condition, defined by a high-to-low transition on SDA
while SCL remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (7-bit address + R/ W bit).The bits
are transferred from MSB down to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
2
C OPERATION
2-wire serial (I
4-wire serial (SPI-compatible) bus
1
Figure 48. ADV7344 Slave Address = 0xD4 or 0xD6
1
2
C-compatible) bus
0
1
0
ALSB/SPI_SS
1
SET UP BY
ADDRESS
CONTROL
2
A1
C-compatible)
READ/WRITE
CONTROL
0
1
WRITE
READ
X
2
C
Rev. 0 | Page 25 of 88
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
occurs when the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted
address. The R/ W bit determines the direction of the data.
Logic 0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first byte
means that the master reads information from the peripheral.
The ADV7344 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/ W bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
updating all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only a start condition, a stop
condition, or a stop condition followed by a start condition. If
an invalid subaddress is issued by the user, the ADV7344 does
not issue an acknowledge and does return to the idle condition.
If the user utilizes the auto-increment method of addressing the
encoder and exceeds the highest subaddress, the following
actions are taken:
•
•
In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge
condition occurs when the SDA line is not pulled low on
the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7344, and the part returns to the idle condition.
ADV7344