adv7344 Analog Devices, Inc., adv7344 Datasheet - Page 48

• Manufacturer Part Number: adv7344
• Description: Multiformat Video Encoder Six 14-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

ADV7344
FEATURES
OUTPUT OVERSAMPLING
The ADV7344 includes two on-chip phase locked loops (PLLs)
that allow for oversampling of SD, ED, and HD video data.
Table 36 shows the various oversampling rates supported in the
ADV7344.
SD Only, ED Only, and HD Only Modes
PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is
unused in these modes. PLL 1 is disabled by default and can be
enabled using Subaddress 0x00, Bit 1 = 0.
SD and ED/HD Simultaneous Modes
Both PLL 1 and PLL 2 are used in simultaneous modes. The use
of two PLLs allows for independent oversampling of SD and
ED/HD video. PLL 1 is used to oversample SD video data, and
PLL 2 is used to oversample ED/HD video data. In simultaneous
modes, PLL 2 is always enabled. PLL 1 is disabled by default and
can be enabled using Subaddress 0x00, Bit 1 = 0.
ED/HD NONSTANDARD TIMING MODE
Subaddress 0x30, Bits[7:3] = 00001
For any ED/HD input data that does not conform to the
standards available in the ED/HD input mode table
(Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard
timing mode can be used to interface to the ADV7344.
ED/HD nonstandard timing mode can be enabled by
setting Subaddress 0x30, Bits[7:3] to 00001.
Table 36. Output Oversampling Modes and Rates
Input Mode
Subaddress 0x01 [6:4]
000
000
001/010
001/010
001/010
001/010
011/100
011/100
011/100
011/100
111
111
Table 37. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition
b → c
c → a
a → b
c → b
1
2
a = tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level.
If P_VSYNC = 1, it should transition to 0. If P_VSYNC = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, P_VSYNC should always be 0.
SD only
SD only
ED only
ED only
HD only
HD only
SD and ED
SD and ED
SD and HD
SD and HD
ED only (at 54 MHz)
ED only (at 54 MHz)
1
P_HSYNC
1 → 0
0
0 → 1
0 → 1
PLL and Oversampling Control
Subaddress 0x00, Bit 1
1
0
1
0
1
0
1
0
1
0
1
0
Rev. 0 | Page 48 of 88
A clock signal must be provided on the CLKIN_A pin.
P_HSYNC and P_VSYNC must be toggled by the user to
generate the appropriate horizontal and vertical synchronization
pulses on the analog output from the encoder. Figure 59 illustrates
the various output levels that can be generated. Table 37 lists the
transitions required to generate these output levels.
Embedded EAV/SAV timing codes are not supported in
ED/HD nonstandard timing mode.
The user must ensure that appropriate pixel data is applied to
the encoder where the blanking level is expected at the output.
Macrovision and output oversampling are not available in
ED/HD nonstandard timing mode.
a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.
b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.
c = SYNCHRONIZATION PULSE LEVEL.
ANALOG
OUTPUT
b
Figure 59. ED/HD Nonstandard Timing Mode Output Levels
c
a
P_VSYNC
1 → 0 or 0
0 → 1
1
0
Oversampling Mode and Rate
SD (2×)
SD (16×)
ED (1×)
ED (8×)
HD (1×)
HD (4×)
SD (2×) and ED (8×)
SD (16×) and ED (8×)
SD (2×) and HD (4×)
SD (16×) and HD (4×)
ED only (at 54 MHz) (1×)
ED only (at 54 MHz) (8×)
BLANKING LEVEL
b
2
ACTIVE VIDEO
b