adv7344 Analog Devices, Inc., adv7344 Datasheet - Page 18

• Manufacturer Part Number: adv7344
• Description: Multiformat Video Encoder Six 14-bit Noise Shaped Video Dacs
• Manufacturer: Analog Devices, Inc.

ADV7344
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 13. Pin Function Descriptions
Pin No.
13, 12,
9 to 2
29 to 25,
18 to 14
62 to 58,
55 to 51
30
63
50
49
22
23
24
48
47
36
45, 35
Mnemonic
Y9 to Y0
C9 to C0
S9 to S0
CLKIN_A
CLKIN_B
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
SFL/MISO
R
R
COMP1,
COMP2
SET1
SET2
Input/
Output
I
I
I
I
I
I/O
I/O
I
I
I
I/O
I
I
O
V
DGND
DD_IO
V
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
C0
C1
C2
DD
10
11
12
13
14
15
16
1
3
9
2
4
5
6
7
8
Description
10-Bit Pixel Port (Y9 to Y0). Y0 is the LSB. Refer to Table 31 for input modes.
10-Bit Pixel Port (C9 to C0). C0 is the LSB. Refer to Table 31 for input modes.
10-Bit Pixel Port (S9 to S0). S0 is the LSB. Refer to Table 31 for input modes.
Pixel Clock Input for HD only (74.25 MHz), ED
Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and Vertical Synchronization Control section.
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is
used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R
AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from R
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from R
Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to V
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
Figure 21. Pin Configuration
SET1
Rev. 0 | Page 18 of 88
(Not to Scale)
ADV7344
TOP VIEW
to AGND.
SET2
to AGND.
1
only (27 MHz or 54 MHz) or SD only (27 MHz).
48
46
40
47
45
44
43
42
41
39
38
37
36
35
34
33
SFL/MISO
R
V
COMP1
DAC 1
DAC 2
DAC 3
V
AGND
DAC 4
DAC 5
DAC 6
R
COMP2
PV
EXT_LF1
SET1
REF
AA
SET2
DD
AA
.
SET1
to