adsp-bf538f Analog Devices, Inc., adsp-bf538f Datasheet - Page 26

• Manufacturer Part Number: adsp-bf538f
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF538/ADSP-BF538F
TIMING SPECIFICATIONS
Table 13
ADSP-BF538/ADSP-BF538F processors’ clocks. Take care in
selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock, system clock, and voltage controlled
Table 13. Core Clock (CCLK) Requirements - 400 MHz Models
Table 14. Core Clock (CCLK) Requirements - 533 MHz Models
Table 15. Phase-Locked Loop Operating Conditions
Table 16. System Clock (SCLK) Requirements
1
2
Parameter
f
Parameter
f
f
f
f
f
Parameter
f
f
f
f
f
f
Parameter
f
f
t
Guaranteed to t
VCO
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SCLK
SCLK
SCLK
(= 1/f
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
and
SCLK
1
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
) must be greater than or equal to t
SCLK
Table 14
Voltage Controlled Oscillator (VCO) Frequency
= 7.5 ns. See
describe the timing requirements for the
DDINT
DDINT
DDINT
DDINT
DDINT
Table 22 on page
= 1.14 V Minimum)
= 1.045 V Minimum)
= 0.95 V Minimum)
= 0.85 V Minimum)
= 0.8 V Minimum)
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
= 0.8 V Minimum)
= 1.2 V Minimum)
= 1.14 V Minimum)
= 1.045 V Minimum)
= 0.95 V Minimum)
= 0.85 V Minimum)
DDINT
DDINT
CCLK
32.
.
≥ 1.14 V)
< 1.14 V)
Rev. A | Page 26 of 56 | January 2008
Internal Regulator
Setting
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Internal Regulator
Setting
1.25 V
1.20 V
1.10 V
1.00 V
0.95 V
0.85 V
Min
50
Max
133
100
2
oscillator (VCO) operating frequencies, as described in
lute Maximum Ratings on Page
locked loop operating conditions.
Requirements.
Unit
MHz
MHz
Max
400
364
333
280
250
Max
533
500
444
400
333
250
Max
Max f
CCLK
Unit
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
25.
Table 16
Table 15
Unit
MHz
lists System Clock
describes phase-
Abso-