adsp-bf538f Analog Devices, Inc., adsp-bf538f Datasheet - Page 34
adsp-bf538f
Manufacturer Part Number
adsp-bf538f
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-BF538F.pdf
(56 pages)
- Current page: 34 of 56
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ADSP-BF538/ADSP-BF538F
Table 24. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Timing Requirement
t
Switching Characteristics
t
t
t
t
t
t
WBR
SD
SE
DBG
EBG
DBH
EBH
ARE
BR
CLKOUT
AMSx
BGH
ABE1-0
AWE
BG
ADDR19-1
BR Pulse Width
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
CLKOUT High to BG High Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
Figure 17. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
t
WBR
Rev. A | Page 34 of 56 | January 2008
t
t
t
SD
SD
SD
t
t
DBG
DBH
Min
2
t
SCLK
t
t
EBG
EBH
Max
4.5
4.5
3.6
3.6
3.6
3.6
t
t
t
SE
SE
SE
Unit
ns
ns
ns
ns
ns
ns
ns
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