adsp-bf538f Analog Devices, Inc., adsp-bf538f Datasheet - Page 31

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adsp-bf538f

Manufacturer Part Number
adsp-bf538f
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
Table 21. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
S = number of programmed setup cycles, WA = number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
DANR
HAA
DDAT
ENDAT
DO
HO
ADDR19–1
DATA15–0
CLKOUT
ABE1–0
AMSx
ARDY
AWE
ARDY Negated Delay from AMSx Asserted
ARDY Asserted Hold After ARE Negated
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
t
ENDAT
SETUP
t
t
DANW
DO
t
DO
Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
WRITE DATA
PROGRAMMED WRITE
ACCESS 2 CYCLES
2
2
Rev. A | Page 31 of 56 | January 2008
BE, ADDRESS
1
EXTENDED
ACCESS
t
HO
1 CYCLE
HOLD
ADSP-BF538/ADSP-BF538F
t
t
HAA
DDAT
Min
0.0
1.0
0.8
t
HO
Max
(S + WA – 2) × t
6.0
6.0
SCLK
Unit
ns
ns
ns
ns
ns
ns

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