mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 169

• Manufacturer Part Number: mc68hc908gr16
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

14.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
LINT — LIN Transmit Enable
LINR — LIN Receiver Bits
Freescale Semiconductor
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
In LIN (version 1.2 and later) systems, the master node transmits a break character which will appear
as 11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Because a slave node cannot know
if it is running faster or slower than the master node (prior to synchronization), the LINR bit allows the
slave node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits.
The break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
Address:
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Table
Table
Reset:
Read:
Write:
LINT
0
0
0
1
1
1
1
14-6.
14-6.
$0019
LINT
Bit 7
0
LINR
0
1
1
0
0
1
1
Figure 14-17. ESCI Baud Rate Register (SCBR)
= Unimplemented
LINR
6
0
M
Table 14-6. ESCI LIN Control Bits
X
0
1
0
1
0
1
MC68HC908GR16 Data Sheet, Rev. 5.0
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
13-bit generation enabled for LIN transmitter
14-bit generation enabled for LIN transmitter
11-bit break detect/13-bit generation enabled for LIN
12-bit break detect/14-bit generation enabled for LIN
SCP1
5
0
NOTE
SCP0
R
4
0
= Reserved
Functionality
R
3
0
SCR2
2
0
SCR1
1
0
SCR0
Bit 0
0
I/O Registers
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