mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 189

• Manufacturer Part Number: mc68hc908gr16
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Interrupt Status Register 2
I14–I7 — Interrupt Flags 14–7
Interrupt Status Register 3
Bits 7–6 — Always read 0
I20–I15 — Interrupt Flags 20–15
15.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
15.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output (see
break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module
to see how each module is affected by the break state.
15.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
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These flags indicate the presence of interrupt requests from the sources shown in
These flags indicate the presence of an interrupt request from the source shown in
1 = Interrupt request present
0 = No interrupt request present
1 = Interrupt request present
0 = No interrupt request present
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
$FE05
$FE06
Bit 7
Bit 7
I14
R
R
R
R
0
0
0
Figure 15-14. Interrupt Status Register 2 (INT2)
Figure 15-15. Interrupt Status Register 3 (INT3)
Chapter 18 Timer Interface Module
= Reserved
= Reserved
I13
R
R
6
0
6
0
0
MC68HC908GR16 Data Sheet, Rev. 5.0
I12
I20
R
R
5
0
5
0
I11
I19
R
R
4
0
4
0
I10
I18
R
R
3
0
3
0
(TIM)). The SIM puts the CPU into the
I17
I9
R
R
2
0
2
0
I16
I8
R
R
1
0
1
0
Table
Bit 0
Bit 0
Table
I15
I7
R
R
0
0
Exception Control
15-3.
15-3.
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