mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 210

no-image

mc68hc908gr16

Manufacturer Part Number
mc68hc908gr16
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc68hc908gr16CFA
Manufacturer:
FREESCALE
Quantity:
2 650
Part Number:
mc68hc908gr16CFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc908gr16CFA
Manufacturer:
FREESCALE
Quantity:
2 650
Part Number:
mc68hc908gr16CFA
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc68hc908gr16CFJ
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc908gr16MFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Peripheral Interface (SPI) Module
16.12.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is 0 and its SS pin is at 0. To support a multiple-slave system,
a 1 on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
16.12.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
16.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
16.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. See
210
16.5 Transmission
MASTER SS
MISO/MOSI
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
Formats.) Since it is used to indicate the start of a transmission, the SS must be
BYTE 1
MC68HC908GR16 Data Sheet, Rev. 5.0
Figure 16-13. CPHA/SS Timing
BYTE 2
Figure
16-13.
16.13.2 SPI Status and Control Register.
BYTE 3
Freescale Semiconductor

Related parts for mc68hc908gr16