mpc860srzp50 Freescale Semiconductor, Inc, mpc860srzp50 Datasheet - Page 10

• Manufacturer Part Number: mpc860srzp50
• Description: Mpc860sar Powerquicc Features
• Manufacturer: Freescale Semiconductor, Inc

ATM Support
Low-power stop disables all logic in the processor except the minimum logic required to restart the device,
and provides the lowest power consumption but requires the longest wake-up time.
1.4
ATM Support
Support for asynchronous transfer mode (ATM) has been integrated into the 860SAR by inclusion of ATM
microcode in the ROM of the CPM and addition of a UTOPIA port, multiplexed onto parallel port D. The
serial communications signals that existed on port D for the standard MPC860 have been multiplexed onto
port A and port C, similarly to the MC68360.
ATM processing is performed in the CPM RISC by microcoded routines. The ATM performance of the
860SAR will vary depending on the mode of the physical interface (serial or UTOPIA) and the protocol
processing performed (AAL0 or AAL5).
The UTOPIA port of the 860SAR is 8 bits wide. Handshaking is performed on a cell basis. The UTOPIA
port has no FIFO; the UTOPIA PHY will contain internal storage so that cells (typically only one cell) will
be held there until the 860SAR is ready to process it, upon which the cell will be transferred all at once. Two
bits of ‘PHY address’ are also included in the UTOPIA port to enable implementation of multi-PHY
UTOPIA for up to 4 PHY devices. If multi-PHY UTOPIA is implemented, external logic will have to
decode these signals in order to gate the transmit and receive cell handshaking signals to and from the
appropriate PHY devices.
The receive channel of the 860SAR has a higher priority than the transmit channel, enabling the (maximum)
70 Mbps ATM bandwidth of the 860SAR to be dynamically switched between the receive and transmit
channels. Thus the 860SAR can be connected to full-duplex high-speed channels (e.g. 51 Mbps) without
loss of cells; the transmit bandwidth will merely drop when the receive port is operating at maximum speed.
For connection to higher-speed UTOPIA connections (e.g. 155 Mbps), an external FIFO will be required,
and the time-average of the bandwidth processed by the 860SAR must be less than 70 Mbps.
Serial-mode ATM can be performed over any of the SCCs for a byte-aligned serial stream only. This means
that an indication of a byte boundary in the serial stream must be given to the 860SAR SCC. With
frame-based transmission (e.g. T1, E1, or ADSL), ATM cells are mapped into n-byte frames at byte
boundaries, and a frame-sync signal is always provided; thus signals in a frame-based format can be
gluelessly connected to the MPC860 via either of the TDM interfaces (TDM
or TDM
). Serial streams that
a
b
have no indication of byte boundaries can only be supported if external logic provides a byte-boundary sync.
The ATM pace control (APC) transmit scheduler is also implemented in microcode. However, a CPM timer
(Timer 4) is also dedicated to generate the clock which is counted by the APC. The speed of this timer
defines the granularity of the control of the APC.
The receive connection table can be implemented either in internal memory or external memory, or with a
combination. Internal memory can be used to support up to 32 connections. Additional connections can be
supported with external memory using address compression, with some loss of performance. It is possible
to use a combination of internal connections and external connections with address compression, enabling
the user to minimize performance loss by keeping the highest-traffic connections in internal memory.
Finally, features also exist to enable use of a content-addressable memory (CAM), to support a large number
of connections in external memory with no performance loss.
Buffer descriptors and buffers for the ATM virtual circuit connections (VCCs) can be contained in internal
or external memory, but will typically be contained in external memory. The ATM microcode uses bursting
DMA to maximize the performance of the ATM connections.
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MPC860SAR PowerQUICC™ Technical Summary
MOTOROLA