mpc860srzp50 Freescale Semiconductor, Inc, mpc860srzp50 Datasheet - Page 9

• Manufacturer Part Number: mpc860srzp50
• Description: Mpc860sar Powerquicc Features
• Manufacturer: Freescale Semiconductor, Inc

The PCMCIA interface is a master (socket) controller and is compliant with release 2.1. The interface
supports up to two independent PCMCIA sockets requiring only external transceivers/buffers. It provides
eight memory or I/O windows that can be allocated to the socket. If only one PCMCIA port is being used,
the unused PCMCIA port may be used as general-purpose input with interrupt capability.
1.2.3
The MPC860 PowerQUICC family, like the earlier generation MC68360 QUICC, implements a
dual-processor architecture. This dual-processor architecture provides both a high-performance,
general-purpose processor for application programming use as well as a special-purpose communication
processor (CPM) uniquely designed for communications needs.
The CPM contains features that allow the PowerQUICC to excel in communications and networking
products. These features may be divided into three subgroups:
The communication processor module provides the communication features of the MPC860 PowerQUICC
family. It includes a RISC processor, four serial communication controllers (SCC), four serial management
controllers (SMC), one serial peripheral interface (SPI), one I
interrupt controller, a time-slot assigner, three parallel ports, a parallel interface port, four independent baud
rate generators, and sixteen serial DMA channels to support the SCCs, SMCs, SPI, and I
The SDMAs provide two channels of general-purpose DMA capability for each communications channel.
They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic.
The four general-purpose timers on the CPM are identical to the timers found on the MC68360 and still
support the internal cascading of two timers to form a 32-bit timer.
The PowerQUICC family maintains the best features of the MC68360 QUICC
required to provide for the increased flexibility, integration, and performance requested by customers
demanding the performance of the PowerPC architecture. Because the CPM architectural approach remains
intact between the PowerQUICC family and the MC68360 QUICC, an MC68360 QUICC user can easily
become familiar with the PowerQUICC.
Additionally, like the MC68MH360 QUICC32 and the MPC860MH, the 860SAR supports the QMC
microcode, enabling it to provide protocol processing for multiple time-division-multiplexed channels over
a single SCC.
1.3
The MPC860 PowerQUICC family supports a wide range of power management features including full-on,
doze, sleep, deep-sleep, and low-power stop. In full-on mode, the MPC860 processor is fully powered with
all internal units operating at the full speed of the processor. There is a gear mode determined by a clock
divider that allows the operating system to reduce the operational frequency of the processor.
Doze mode disables core functional units except the time base, decrementer, PLL, memory controller,
real-time clock, and places the communication processor module in low-power standby mode. Sleep mode
disables everything except the real-time clock and periodic interrupt timer, thus leaving the PLL active for
quick wake-up. The deep-sleep mode then disables the PLL for lower power, but slower wake-up.
MOTOROLA
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Communications processor (CP)
Sixteen independent serial DMA (SDMA) controllers
Four general-purpose timers
Power Management
Communications Processor Module (CPM)
MPC860SAR PowerQUICC™ Technical Summary
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