mpc860srzp50 Freescale Semiconductor, Inc, mpc860srzp50 Datasheet - Page 4

• Manufacturer Part Number: mpc860srzp50
• Description: Mpc860sar Powerquicc Features
• Manufacturer: Freescale Semiconductor, Inc

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System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— decrementer defined by the PowerPC Architecture
— Time base and real-time clock defined by the PowerPC Architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Memory controller (eight banks)
— Contains complete dynamic random-access memory (DRAM) controller
— Each bank can be a chip-select or RAS to support a DRAM bank
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes, 32 Kbyte to 256 Mbyte
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Interrupts
— Seven external interrupt request (IRQ) lines
— Twelve-port pins with interrupt capability
— Sixteen internal interrupt sources
— Programmable priority between SCCs
— Programmable highest-priority request
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— Supports eight memory or I/O windows
(SDRAM), static random-access memory (SRAM), electrically programmable read-only
memory (EPROM), Flash EPROM, etc.
MPC860SAR PowerQUICC™ Technical Summary
MOTOROLA