mpc860srzp50 Freescale Semiconductor, Inc, mpc860srzp50 Datasheet - Page 3

• Manufacturer Part Number: mpc860srzp50
• Description: Mpc860sar Powerquicc Features
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
•
— Supports 53-byte or up to 64-byte (expanded) ATM cells
— AAL5 segmentation and reassembly (SAR) features for segmentation
— AAL5 segmentation and reassembly (SAR) features for reassembly:
— AAL0 features for transmit include the following:
— AAL0 features for receive include the following:
Embedded MPC860SAR core with 66 MIPS at 50 MHz (using Dhrystone 2.1)
— Single issue, 32-bit version of the embedded MPC860SAR core (fully compatible with
— Advanced on-chip emulation debug mode
— Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
— Thirty-two address lines
— Completely static design (0-MHz to 50-MHz operation)
– Segment CPCS_PDU directly from system memory
– CPCS_PDU padding
– CRC32 generation
– Automatic last cell marking (in PTI field of cell header)
– Automatic CS_UU, CPI, and LENGTH insertion in last cell
– Reassembles CPCS_PDU directly into system memory
– Removes CPCS_PDU padding
– CRC32 checking
– CS_UU, CPI, and LENGTH reporting
– CLP and congestion reporting
– Interrupts per buffer or per message
– Error reporting, including CRC, length mismatch, message abort
– Transmits user-defined cell from transmit emory buffer
– Automatic HEC generation
– Optional CRC10 insertion
– Copies entire cell into receive memory buffer
– Provides interrupt per cell
– Optional CRC10 checking
PowerPC user instruction set architecture definition) with 32- x 32-bit fixed-point registers
– Performs branch folding and branch prediction with conditional prefetch, but without
– 4-Kbyte data cache and 4-Kbyte instruction cache, each with an MMU
– Instruction and data caches are two-way, set associative, physical address, 4-word line
– Memory management units (MMUs) with 32-entry translation lookaside buffers (TLBs)
– MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
conditional execution
burst, least-recently used (LRU) replacement algorithm, lockable on-line granularity
and fully-associative instruction and data TLBs
8 Mbytes; 16 virtual address spaces and 8 protection groups
MPC860SAR PowerQUICC™ Technical Summary
3