mpc860srzp50 Freescale Semiconductor, Inc, mpc860srzp50 Datasheet - Page 7

• Manufacturer Part Number: mpc860srzp50
• Description: Mpc860sar Powerquicc Features
• Manufacturer: Freescale Semiconductor, Inc

The 860SAR is comprised of three modules that use the 32-bit internal bus—embedded MPC860SAR core,
system integration unit (SIU), and the communication processor module (CPM). See Figure 1. for the
860SAR block diagram.
Note: Changes from MPC860 are shaded.
1.2.1
The embedded MPC860SAR core is compliant with the PowerPC user instruction set architecture
definition. It has a fully-static design that consists of two functional blocks—the integer block and the
load/store block. It executes all integer and load/store operations directly on the hardware. The core supports
integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. Its interface to the internal
and external buses is 32 bits. The core uses a two-instruction load/store queue, a four-instruction prefetch
queue, and a six-instruction history buffer. The core performs branch folding and branch prediction with
conditional prefetch, but without conditional execution. The core can operate on 32-bit external operands
with one bus cycle.
The integer block supports 32- x 32-bit fixed-point general-purpose registers. It can execute one integer
instruction on each clock cycle. Each element in the integer block is only clocked when valid data is present
in the data queue ready for operation, which assures that the power consumption of the device is held to the
absolute minimum required to perform an operation.
The embedded MPC860SAR core is integrated with the memory management units (MMUs) and 4-Kbyte
instruction and data caches. The MMUs provide a 32-entry, fully-associative instruction and data TLB, with
multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and 8 Mbytes. It supports 16 virtual
MOTOROLA
8 Bit
Embedded
MPC8xx
Embedded MPC860SAR Core
Core
Interface
Utopia
SCC1
Load/Store
Instruction
Figure 1. . MPC860SAR PowerQUICC Block Diagram
Interface Port
Parallel I/O
Generators
Baud Rate
Bus
Bus
MPC860SAR PowerQUICC™ Technical Summary
Parallel
SCC2 SCC3 SCC4 SMC1 SMC2
Time Slot Assigner
D Cache
4- Kbyte
4- Kbyte
I Cache
Timers
32-Bit RISC µController
Timer
MMU
MMU
D
4
and Program ROM
I
Controller
Interrupt
Unified Bus
Serial Interface
Micro-Code
Dual-Port
SPI
RAM
ATM
I2C
System Integration Unit
Channels
Channels
16 Serial
2 Virtual
IDMA
DMA
and
Comm unication
Memory Controller
PCMCIA Interface
Bus Interface Unit
System Functions
Real-Time Clock
Processor
Module
32 Bit
32 Bit
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