mpc860srzp50 Freescale Semiconductor, Inc, mpc860srzp50 Datasheet - Page 8

• Manufacturer Part Number: mpc860srzp50
• Description: Mpc860sar Powerquicc Features
• Manufacturer: Freescale Semiconductor, Inc

MPC860SAR Architecture Overview
address spaces with eight protection groups. Three special registers are available as scratch registers to
support software table walk and update.
The instruction cache is 4 Kbytes, two-way, set associative with physical addressing. It allows single-cycle
access on hit with no added latency for miss. It has four words per line and supports burst linefill using a
least recently used (LRU) replacement algorithm. The cache can be locked on a line basis for
application-critical routines. The data cache is 4 Kbytes, two-way, set associative with physical addressing.
It allows single-cycle access on hit with one added clock latency for miss. It has four words per line and
supports burst linefill using an LRU replacement algorithm. The cache can be locked on a line basis for
application-critical routines and can be programmed to support copy-back or write-through via the MMU.
The inhibit mode can be programmed per MMU page.
The embedded MPC860SAR core with its instruction and data caches delivers approximately 66 MIPS at
50 MHz (using Dhrystone 2.1) based on the assumption that it is issuing one instruction per cycle with a
cache hit rate of 94%.
The embedded MPC860SAR core contains a much improved debug interface that provides superior debug
capabilities without causing any degradation in the speed of operation. This interface supports six
watchpoint pins that are used to detect software events. Internally it has eight comparators, four of which
operate on the effective address on the address bus. The remaining four comparators are split, with two
comparators operating on the effective address on the data bus and two comparators operating on the data
on the data bus. The embedded MPC860SAR core can compare using =, , <, > conditions to generate
watchpoints. Each watchpoint can then generate a breakpoint that can be programmed to trigger in a
programmable number of events.
1.2.2
System Interface Unit (SIU)
The SIU on the MPC860 PowerQUICC family integrates general-purpose features useful in almost any
32-bit processor system, enhancing the performance provided by the system integration module (SIM) on
the MC68360 QUICC device.
Although the embedded MPC860SAR core is always a 32-bit device internally, it may be configured to
operate with an 8-, 16- or 32-bit data bus. Regardless of the choice of the system bus size, dynamic bus
sizing is supported, which allows 8-, 16-, and 32-bit peripherals and memory to coexist in the 32-bit system
bus. The SIU also provides power management functions, reset control, decrementer, time base and
real-time clock.
The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM,
SSRAM, EPROM, Flash EPROM, SRDRAM, EDO and other peripherals with two-clock access to external
SRAM and bursting support. It provides variable block sizes from 32 Kbytes to 256 Mbytes. The memory
controller provides 0 to 15 wait states for each bank of memory and can use address type matching to qualify
each memory bank access. It provides four byte-enable signals for varying width devices, one output enable
signal, and one boot chip-select available at reset.
The DRAM interface supports 8-, 16-, and 32-bit ports. Memory banks can be defined in depths of 256
Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes, 32 Mbytes, or 64 Mbytes for all
port sizes. In addition, the memory depth can be defined as 64 Kbytes and 128 Kbytes for 8-bit memory or
128 Mbytes and 256 Mbytes for 32-bit memory. The DRAM controller supports page mode access for
successive transfers within bursts. The MPC860 supports a glueless interface to one bank of DRAM while
external buffers are required for additional memory banks. The refresh unit provides CAS before RAS, a
programmable refresh timer, refresh active during external reset, disable refresh modes, and stacking for a
maximum of seven refresh cycles. The DRAM interface uses a programmable state machine to support
almost any memory interface.
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MPC860SAR PowerQUICC™ Technical Summary
MOTOROLA