s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet
s1r72900
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s1r72900 Summary of contents
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... MF1449 - 01 IEEE1394 Controller IEEE1394 Controller S1R75801F00A S1R72900F00A Technical Manual Technical Manual ...
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NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson ...
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The information of the product number change Starting April 1, 2001 the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative. Configuration ...
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DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. BLOCK DIAGRAM ............................................................................................................................................. 2 4. PIN LAYOUT ..................................................................................................................................................... 3 5. PIN ASSIGNMENT TABLE ................................................................................................................................ 4 6. PIN DESCRIPTION ........................................................................................................................................... 7 7. FUNCTIONAL DESCRIPTION .......................................................................................................................... 9 7.1 Control Register ......................................................................................................................................... 9 7.2 ...
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... PHY/LINK interface circuit • High-speed DS encoder • Supports the short bus reset function at detection of LINK layer IC power-off. • Single 3.3-V power supply • 64-Pin Plastic QFP • Designed with the low-power CMOS technology. * This product is not radioresistant. EPSON S1R72900F00A 1 ...
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... S1R72900F00A 3. BLOCK DIAGRAM LPS Link SCLK Interface LREQ CTL[0:1] D[0:7] BCLKON PS0,PS1,PS2 BCLKON XRST (Power On Reset DS-Link Encoder/Decoder Control Unit 393.216MHz CLK PLL EPSON Cable CPS Power Status TpBias1 TpBias2 TpBias Gen. R1 Voltage- Current R0 Gen TpA1 Transmitter & TpB1 Receiver TpA2 Transmitter & ...
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... XRST 53 FC0 54 FC1 OSCV OSCV Rev. 1.0 SPC7290F0A EPSON S1R72900F00A TEST1 28 TEST0 27 XTEST_MODE CPS 23 DIRECT 22 PS0 21 PS1 20 PS2 19 BCLKON ...
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... S1R72900F00A 5. PIN ASSIGNMENT TABLE The items listed on the pin assignment table are as follows: PIN No. Pin number PIN NAME Pin name of the SIR72900F00A POWER Supply voltage for each I/O cell PLANE OSCV I/O ATTR Type of I/O cells Output pin I/O : Input/output pin P : Power pin ...
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... – – – SS EPSON S1R72900F00A DRIVE(mA) TERM( ) 3.3V 3.3V IOH – – – –6 6 – –2 2 – –6 6 – –6 6 – –6 6 – –6 6 – –6 6 – –6 6 – –6 6 – ...
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... S1R72900F00A PIN No. PIN NAME XRST 54 FC0 55 FC1 OSCV OSCV POWER I/O PLANE ATTR IOL AV – – – – – – ...
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... Configured according to the isolation barrier configuration between PHY and DIRECT LINK. Connect this pin to V capacitor AC connection. Rev. 1.0 Function 30,31,42,51,52 32,33,39,48,49,50 16,25,26,62 17,18,63,64 during normal SS 10,11,12,13 20,21,22 for DC or single DD EPSON S1R72900F00A Pin No. Pin typ. I/O Supply – Supply – 56 Supply – 57 Supply – Supply – Supply – 61 Supply – ...
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... S1R72900F00A Pin name Test pin XTEST_MODE Connect this pin to V operation. Reset pin The SIR72900F00A is initialized when this pin is set to 0. XRST After turning on the power supply, for at least 2ms, maintain XRST = 0. Set this pin to 1 during normal operation. Cable Power Status detection pin ...
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... RegisterB RegisterC RegisterD RegisterE RegisterF R/W Power Reset Value R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 EPSON S1R72900F00A Gap_count Total_ports Delay Power_class Port_Select Description Root Hold Bit Initiate Bus Reset Gap Count_bit0 Gap Count_bit1 Gap Count_bit2 Gap Count_bit3 Gap Count_bit4 Gap Count_bit5 ...
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... S1R72900F00A 7.1.2.2 Register 1 Address Bit Symbol 0x01 0: RHB 1: IBR 2: Gap_count [0] 3: Gap_count [1] 4: Gap_count [2] 5: Gap_count [3] 6: Gap_count [4] 7: Gap_count [5] Bit 0: Root Hold Bit This bit is set automatically by PHY configuration packet transmission. When this bit is '1 request that the node should be the root at the next bus reset. ...
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... The relationships between the bits and pins PS0, PS1, and PS2 are as follows: bit5:PS0(Pin22) bit6:PS1(Pin21) bit7:PS2(Pin20) Rev. 1.0 R/W Power Reset Value R/W 1 R/W See discription R/W 0 R/W 0 R/W 0 EPSON S1R72900F00A Description Link Control Contender Jitter Jitter Jitter Power Class Power Class Power Class 11 ...
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... S1R72900F00A 7.1.2.6 Register 5 Address Bit Symbol 0x05 0: Watchdog 1: ISBR 2: Loop 3: Pwr_fail 4: Timeout 5: Port_event 6: Enab_accel 7: Enab_multi Bit 0: Watchdog When set to '1,' this bit communicates the status of Loop, Power_fail, and Arb_timeout to the Link layer controller IC, regardless of the status of the PHY/LINK interface. When a resume action starts on any port, this bit sends a resume interrupt signal regardless of the value of Int_enable ...
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... When the Page_select bit selects Port Status Page, these bits specify what port between 1000b and 1111b of the PHY register should be accessed. Rev. 1.0 R/W Power Reset Value R/W Power Reset Value R/W 0 R R/W 0 R/W 0 R/W 0 R/W 0 EPSON S1R72900F00A Description Description 13 ...
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... S1R72900F00A Name Address Register00 1000 Register01 1001 Register02 1010 Register03 1011 Register04 1100 Register05 1101 Register06 1110 Register07 1111 7.1.3 Page_select 0 bits 7.1.3.1 Register 00 Address Bit Symbol 0x08 0: Astat [0] 1: Astat [1] 2: Bstat [0] 3: Bstat [1] 4: Child 5: Connected 6: Bias 7: Disabled Bits Status of TPA These bits indicate the status of TPA ...
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... Reserved 7: Reserved Bits Reserved Rev. 1.0 R/W Power Reset Value R 0 Negotiated speed R 0 Negotiated speed R 0 Negotiated speed R/W 0 Enable port event interrupt R/W 0 fault R/W Power Reset Value EPSON S1R72900F00A Description Description 15 ...
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... S1R72900F00A 7.1.3.4 Register 03 Address Bit Symbol 0x0B 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits Reserved 7.1.3.5 Register 04 Address Bit Symbol 0x0C 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits Reserved 7.1.3.6 Register 05 Address Bit Symbol 0x0D 0: Reserved 1: Reserved 2: Reserved ...
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... Bit Symbol 0x0F 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits Reserved Rev. 1.0 R/W Power Reset Value R/W Power Reset Value EPSON S1R72900F00A Description Description 17 ...
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... S1R72900F00A Name Address Register10 1000 Register11 1001 Register12 1010 Register13 1011 Register14 1100 Register15 1101 Register16 1110 Register17 1111 7.1.4 Page_select 1 bits 7.1.4.1 Register 10 Address Bit Symbol 0x08 0: Compliance_level [0] 1: Compliance_level [1] 2: Compliance_level [2] 3: Compliance_level [3] 4: Compliance_level [4] 5: Compliance_level [5] 6: Compliance_level [6] 7: Compliance_level [7] Bits Compliance Level Normally, 1 ('01h') for P1394a-compliant is read ...
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... Power Reset Value R 0 Vendor_ID_bit8 R 0 Vendor_ID_bit9 R 0 Vendor_ID_bit10 R 0 Vendor_ID_bit11 R 0 Vendor_ID_bit12 R 0 Vendor_ID_bit13 R 0 Vendor_ID_bit14 R 0 Vendor_ID_bit15 R/W Power Reset Value R 0 Vendor_ID_bit0 R 1 Vendor_ID_bit1 R 0 Vendor_ID_bit2 R 0 Vendor_ID_bit3 R 1 Vendor_ID_bit4 R 0 Vendor_ID_bit5 R 0 Vendor_ID_bit6 R 0 Vendor_ID_bit7 EPSON S1R72900F00A Description Description Description 19 ...
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... S1R72900F00A 7.1.4.6 Register 15 Address Bit Symbol 0x0D 0: Product_ID [16] 1: Product_ID [17] 2: Product_ID [18] 3: Product_ID [19] 4: Product_ID [20] 5: Product_ID [21] 6: Product_ID [22] 7: Product_ID [23] Bits Product ID [16:23] For the SIR72900F00A, '00h' is read. 7.1.4.7 Register 16 Address Bit Symbol 0x0E 0: Product_ID [8] 1: Product_ID [9] 2: Product_ID [10] 3: Product_ID [11] ...
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... Bits Reserved Rev. 1.0 Table 7.3 Registers of Page_Select R/W Power Reset Value R/W 0 R/W 0 R/W Power Reset Value EPSON S1R72900F00A RemSCLk HostIsbr Description Remain SCLK Host Isbr Description 21 ...
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... S1R72900F00A 7.1.5.3 Register 72 Address Bit Symbol 0x0A 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits Reserved 7.1.5.4 Register 73 Address Bit Symbol 0x0B 0: Reserved 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: Reserved 6: Reserved 7: Reserved Bits Reserved 7.1.5.5 Register 74 Address Bit Symbol 0x0C 0: Reserved 1: Reserved 2: Reserved ...
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... Bits Reserved Rev. 1.0 R/W Power Reset Value R/W Power Reset Value R/W Power Reset Value EPSON S1R72900F00A Description Description Description 23 ...
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... S1R72900F00A 7.2 Data Format 7.2.1 Self-ID packet The Self-ID packets the SIR72900F00A transmits are 2-quadlet packets in the format shown in Figure 7.1. The SIR72900F00A transmits the following Self-ID packet during Self-ID period of bus initialization. The SIR72900F00A also transmits a Self-ID packet automatically as a response to a Ping packet. ...
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... Figure 7.3 PHY Configuration packet format type(0) 00 0000 logical inverse of first quadlet Figure 7.4 Ping packet format type(1/5h) page port logical inverse of first quadlet Figure 7.5 Remote Access packet format EPSON S1R72900F00A 0000 0000 0000 0000 0000 0000 0000 0000 0000 reg reserved 25 ...
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... S1R72900F00A 7.2.4.3 Remote Reply Packet 00 phy-ID 00 7.2.4.4 Remote Command Packet 00 phy-ID 00 Figure 7.7 Remote Command packet format 7.2.4.5 Remote Confirmation Packet 00 phy-ID 00 Figure 7.8 Remote Confirmation packet format 7.2.4.6 Resume Packet 00 phy- type(3/7h) page port logical inverse of first quadlet Figure 7.6 Remote Reply packet format type(8h) 000 ...
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... Figure 7.11 shows an example of outer shield circuit of the cable port. 1M Rev. 1.0 PHYV DD VF=0.4V CPS 1 F TPBIAS 56 56 TPA P TPA N TPB P TPB 240pF 5.1k Figure 7.10 Cable port interface circuit OUTER CABLE SHIELD 0.01 F 0.01 F Figure 7.11 Cable port outer shield circuit EPSON S1R72900F00A 240k CABLE POWER TWIST PAIR A TWIST PAIR B OUTER SHIELD TERMINATION 27 ...
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... S1R72900F00A Cables specifically designed as per IEEE 1394 are used as media for the cable port interface. Data is transmitted through two shielded pairs of twisted cables. As shown in Figure 7.10, each twisted pair cable is connected to the TpB pair of the node to which the TpA pair of the own node. ...
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... IC, which correspondent to the upper level layer of its own node. Either way, the Remote Confirmation packet is transferred to all ports and the PHY/LINK interface when the S1R72900F00A receives the Remote Command packet. Bus reset is then issued to all ports other than the port (Suspend Initiator) that the Suspend bit is set to, and the node enters the reset state ...
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... For AC connection (with a single capacitor), also connect the DIRECT pin to V Link Figure 7.14 SIR72900F00A -to-Link chip connection diagram (AC connection shown in Figure 7.13. DD SCLK LREQ D[0:7] CTL[0:1] PHY S1R72900 LPS LINKON V DD DIRECT . DD SCLK LREQ D[0:7] CTL[0:1] PHY S1R72900 LPS LINKON V DD DIRECT EPSON Rev. 1.0 ...
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... As shown in Figure 7.15, use a 1000-pF coupling capacitor for AC connection. * The SIR72900F00A is not in support of the IEEE1394 specification Annex J isolation barrier. Bus Holder Rev. 1.0 C=1000pF Figure 7.15 AC coupling connection EPSON S1R72900F00A Bus Holder 31 ...
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... When the S1R72900F00A detects LPS = HIGH after the PHY/LINK interface was reset and set to disable, SCLK output starts after the disable state. If the PHY/LINK interface uses the DC connection, the S1R72900F00A outputs LOW to the 7 SCLK cycles CTL, D after detecting LPS, and outputs Receive (CTL[0:1] = 10b, D[0.7]=ffh) for Data Prefix to the PHY/LINK interface at the 8th SCLK, returning to normal operation ...
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... The S1R72900F00A issues short bus reset (SBR) against other nodes connected when detecting LPS = "1". This function makes cancellation possible by clearing Page select7Register 70 bit 7. A typical external circuit for the LPS pin is shown in Figures 7.17, 18 and 19. Figure 7.17 A typical direct connection and LPS external circuit 1 (with external signal control) Figure 7 ...
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... S1R72900F00A LPS pin Figure 7.19 A typical AC connection and LPS external circuit 34 PHY V DD 10k LPS control signal 10k EPSON Rev. 1.0 ...
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... Grants the Link the right to control the PHY/LINK interface for packet transmission. Description Completes the packet transmission and frees the PHY/LINK interface. · Holds the PHY/LINK interface until the data on the packet to be transmitted is determined. · Requests concatenated packet transmission. Transmits data on the transmitted packet to the PHY. Reserved. EPSON S1R72900F00A 35 ...
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... S1R72900F00A 7.4.4.1 LREQ To request packet transmission, access to the PHY register, or acceleration control, the Link layer controller IC inputs a serial signal synchronized with SCLK to the LREQ pin. The serial signal contains information on the request type, speed of the packet to be transmitted, and read/write command. The length of the LREQ serial signal varies depending on the type of the request bits for acceleration control requests, 7 bits for bus requests, 9 bits for register read requests, and 17 bits for register write requests ...
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... When this bit is '1,' arbitration acceleration can be enabled. Represents the completion of transmission. Always '0'. Table 7.13 Request type Description Immediate request Isochronous request Priority request Fair request Read data from the configured register Write data in the configured register Represents that PHY arbitration acceleration is disabled/enabled. Reserved EPSON S1R72900F00A 37 ...
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... S1R72900F00A As soon as the reception of a register write request completes, the SIR72900F00A changes the data at the address. On receiving a register read request, the SIR72900F00A outputs the data at the address to the Link layer controller status transmission. If the output is interrupted by packet reception/transmission, the SIR72900F00A repeats the status output from the first bit until the output completes ...
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... Figure 7.22 Transmit EPSON S1R72900F00A ...
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... S1R72900F00A Having input the final bit of the packet data, the Link layer controller IC inputs Idle ('00b') or Hold ('01b') for one SCLK cycle and Idle for another SCLK cycle. Then the SIR72900F00A takes over the control of the PHY/LINK interface. This Hold ('01b') bit ensures that the Link layer controller IC transmits the next packet without giving up the serial bus (concatenated packet) ...
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... PHY Drive CTL[0: D[0: Rev. 1 Figure 7.23 Receive Table 7.15 Speed code (SP[0:7]) D[0:7] Data Rate 00xxxxxxb 100Mbps 0100xxxxb 200Mbps 01010000b 400Mbps EPSON S1R72900F00A ...
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... S1R72900F00A 7.5 Oscillating Circuit The SIR72900F00A carries a built-in crystal oscillation circuit. The output frequency of the external quarts oscillator should be 24.576MHz ( 80ppm (including the temperature characteristics). As the quarts oscillator, we recommend our MA-406 (24.576MHz 10pF) to secure the necessary frequency precision. Position the quarts oscillator and capacitor in the neighborhood of this IC and maintain the wiring pattern as short as possible ...
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... Operating temperature Rev. 1.0 Table 8.1 Absolute maximum ratings Symbol Rating V –0 –0 –0 OUT I OUT T –65 to 150 STG Symbol Min. Typ. V 3.00 3. EPSON S1R72900F00A (V =0V) SS Unit ˚C Max. Unit 3.60 V – – 70 ˚C 43 ...
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... S1R72900F00A 8.3 DC Characteristics Item Power supply current (S400 packet transmission together with port 0.1) Supply current Static current Supply current Input leak Pin name: LREQ,CTL0,CTL1,D0 to 7,PD,LPS,BCLKON,XDIRECT,CPS,TPA*,TPB*,XRST,XI Input leak current Input characteristics (CMOS) High level input voltage V Low level input voltage V Schmidt input characteristics 1 ...
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... Pin name: LREQ,CTL0,CTL1 7,LPS, V =3. BHH V =2. =3. BHL V =0.4 IN VDD=3.6V BHHO IIL=–0.9mA V =3.6V DD BHLO I =0.9mA IL EPSON S1R72900F00A Min. Typ. Max. V –0.4 DD 0.4 V –0.4 DD 0.4 –1 1 –0.3 0 –0.4 DD Unit ...
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... S1R72900F00A Item Cable interface Common mode input voltage V Common mode input voltage V Common mode output voltage V Common mode output current I Common mode output current I Common mode output current I Differential input voltage amplitude Differential output voltage amplitude Arb comparator threshold voltage (+) Arb comparator threshold voltage (– ...
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... DC judgment level 8.4.2 Clock timing SCLK tscc1 BCLKON T LINKON Symbol t scyc t SCLKHIGH pulse width sccl t SCLK LOW pulse width scd T LINKON Rev. 1.0 tscyc tscd Min. SCLK cycle 20.343 9.16 9.16 BCLKON cycle 125 EPSON S1R72900F00A Typ. Max. Unit 20.345 20.346 ns 11.18 ns 11.18 ns 250 ns 47 ...
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... S1R72900F00A 8.4.3 PHY/LINK interface timing SCLK T D Output Timing CTL[0: D[0:7] Intput Timing CTL[0:1] D[0:7] Symbol T CTL. D delay time D T CTL. D. LREQ setup time SU T CTL. D. LREQ hold time H 8.4.4 Cable interface timing Symbol TJITTER TSKEW rise time and fall time ...
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... XRST XTET_MODE FC0 FC1 S1R72900F00A DIRECT OSCV OSCV DD BCLKON EPSON S1R72900F00A 0.001 F 0 0.001 TEST1 29 1k TEST0 28 27 0.001 0.001 240k DD Cable Power CPS ...
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... S1R72900F00A 10. OUTLINE DIMENSIONS Plastic QFP13-64 pin –0.4 10 –0 INDEX 1 16 0.18 0.5 EPSON 32 17 +0.1 -0.05 +0.05 0.125 -0.025 0ß 10ß 0.5 –0.2 1 Unit:mm Rev. 1.0 ...
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... International Sales Operations AMERICA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone : +1-408-922-0200 Fax : +1-408-922-0238 SALES OFFICES West 1960 E. Grand Avenue El Segundo, CA 90245, U.S.A. Phone : +1-310-955-5300 Fax : +1-310-955-5400 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. ...
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In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings. ...
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... S1R72900F00A Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue September,2001 Printed in Japan H A ...