s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 36

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

S1R72900F00A
7.4.2 LPS (Link Power Status)
By inputting to the LPS pin, the S1R72900F00A is set to enable/disable the PHY/LINK interface. If the S1R72900F00A
detects LPS = LOW during a TLPS RESET period, the PHY/LINK interface is set to the disable state to output LOW
to the SCLK, CTL0-1 and D0-7. (While LOW is set when the PHY/LINK interface is DC connection, "Hi-Z" is set when
it is AC connection.)
However, if Page select7 Register 70 bit 6 was set, SCLK is not terminated and continues to output a clock signal even
when the PHY/LINK interface is set to disable.
If the PHY/LINK interface was reset, all bus requests and register read requests are cancelled. Also, the S1R72900F00A
recognizes that the packet transfer was terminated and operates, if the Link layer controller IC reset the PHY/LINK
interface during packet transfer.
When the PHY/LINK interface is set to disable period, the status output is not operated, therefore, this information is
not output even after the PHY/LINK interface is set to enabled.
When the S1R72900F00A detects LPS = HIGH after the PHY/LINK interface was reset and set to disable, SCLK output
starts after the disable state.
If the PHY/LINK interface uses the DC connection, the S1R72900F00A outputs LOW to the 7 SCLK cycles CTL, D
after detecting LPS, and outputs Receive (CTL[0:1] = 10b, D[0.7]=ffh) for Data Prefix to the PHY/LINK interface at
the 8th SCLK, returning to normal operation.
For AC connection, the S1R72900F00A outputs LOW to the 1SCLK cycle period CTL,D within 1 to 6 SCLK cycles
after detecting LPS, returning to normal operation. Other periods will become "Hi-Z".
In this case, it continues to output Receive for Data Prefix to the PHY/LINK interface until packet receiving is
terminated if its node is receiving a packet.
32
T
T
LPS_DISABLE
LPS_RESET
Symbol
T
T
LPSH
LPSL
LPS
LPS low time (pulses)
LPS high time (pulses)
The time required until the SIR72900F00A detects
LPS = 0 and resets the PHY/LINK interface.
The time required until the SIR72900F00A detects
LPS = 0 and disables the PHY/LINK interface.
Figure 7.16 LPS waveforms in AC connection
T
LPSH
Table 7.5 LPS timing
Item
EPSON
T
LPSL
Min.
0.09
0.09
1.2
25
Max.
2.75
1.0
1.0
30
Unit
Rev. 1.0
m
m
m
m