s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 40

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

S1R72900F00A
7.4.4.1 LREQ
To request packet transmission, access to the PHY register, or acceleration control, the Link layer controller IC inputs
a serial signal synchronized with SCLK to the LREQ pin.
The serial signal contains information on the request type, speed of the packet to be transmitted, and read/write
command.
The length of the LREQ serial signal varies depending on the type of the request. It is 6 bits for acceleration control
requests, 7 bits for bus requests, 9 bits for register read requests, and 17 bits for register write requests.
The serial signal must contain '0' as a stop bit at the end.
A packet transmission request uses the 7-bit-long format as shown in Table 7.8.
A read PHY chip register request uses the 9-bit-long format as shown in Table 7.10. A write register request uses the
17-bit-long format as shown in Table 7.11.
36
Bit(s)
1 to 3
4 to 5
Bit(s)
1 to 3
4 to7
0
6
0
8
Request Speed Represents the packet transmission speed.
Request Type
Request Type
Address
Start Bit
Stop Bit
Start Bit
Stop Bit
Typ.
Typ.
LR0
LR1
Represents the start of transmission. Always '1'.
Represents the request type as shown in Figure 7.13.
Represents the completion of transmission. Always '0'.
Represents the start of transmission. Always '1'.
Represents the request type as shown in Figure 7.13.
Represents the completion of transmission. Always '0'.
Represents the address of the PHY register to be transmitted.
Table 7.10 Read register format
LR2
LREQ[4:5]
Figure 7.20 LREQ stream
Table 7.8 Request format
Table 7.9 Speed format
00
01
10
11
LR3
EPSON
LR4
Description
Description
Data Rate
Reserved
100Mbps
200Mbps
400Mbps
LRn-1
LRn
LRn=LREQn
Rev. 1.0