s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 13

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

7. FUNCTIONAL DESCRIPTION
7.1 Control Register
7.1.1 Accessing the register
The registers on the SIR72900F00A are accessed from the Link layer controller IC. For details, see Section 7.4.4 Link
interface.
7.1.2 Register bits
This section explains the control register bits of the SIR72900F00A. In the R/W column, R means read only and R/W
means readable/writable. The Power Reset Value column shows the initial value (0 or 1) which each bit takes after
power-on reset.
7.1.2.1 Register 0
Bits 0 to 5: Physical Node ID
Bit 6: Root Indicator
Bit 7: Cable Power Status
Rev. 1.0
This register address 00h is output as a status to the PHY/LINK interface after transmission of a Self-ID packet. These
bits indicate Node IDs that were determined during a Self-ID period and they are determined when transmitting a Self-
ID packet during a Self-ID period. These bits are initialized by bus reset (BR).
This bit is determined during a Tree-ID period and it indicates the root setting for its node.
When this bit is '1', this node is set as the root and initialized by bus reset.
This bit indicates the cable power supply status reflecting the status of the CPS pin.
When this bit is '1', it indicates that the power is supplied through the cable.
Register0
Register1
Register2
Register3
Register4
Register5
Register6
Register7
Address
Name
0x01
–
–
–
–
–
–
–
–
0: RHB
1: IBR
2: Gap_count [0]
3: Gap_count [1]
4: Gap_count [2]
5: Gap_count [3]
6: Gap_count [4]
7: Gap_count [5]
Address
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bit Symbol
Watchdog ISBR
RHB
LCtrl
0
Page_Select
Max_speed
Extended
Contender
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IBR
1
Table 7.1 Registers
Power Reset Value
EPSON
Loop
Physical_ID
2
0
0
1
1
1
1
1
1
Pwr_fail Timeout Port_event Enab_accel Enab_multi
Jitter
3
RegisterC
RegisterD
RegisterA
RegisterB
RegisterE
RegisterF
Register8
Register9
Gap_count
4
Root Hold Bit
Initiate Bus Reset
Gap Count_bit0
Gap Count_bit1
Gap Count_bit2
Gap Count_bit3
Gap Count_bit4
Gap Count_bit5
Port_Select
Total_ports
5
Description
Delay
Power_class
R
S1R72900F00A
6
PS
7
9