hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 11

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

Output Data Port Modes
The HMP8112A can output data in 2 formats, an 8-bit Pixel
Transfer Mode and a 16-bit Pixel Transfer mode.
16-Bit Pixel Transfer Mode
In 16-bit Pixel Transfer Mode pixel data is output at the CLK
frequency and Table 3 shows the number of data points per
video line to expect for a given standard. Data is output as
4:2:2 subsampled data in a Y-Cb/Y-Cr 16-bit sequence. The
Data Valid (DVLD) flag is asserted when video data is
present on the 16-bit output port (Y[7:0], CbCr[7:0]). The
luminance data is output on Y[7:0] bus. Chrominance data is
sequenced on the CbCr[7:0] bus, starting with Cb and then
Cr. Per Figure 13, the ACTIVE flag is asserted when the
active video portion of the horizontal scan line is present on
the data output port. See Figure 14 for 16-Bit Pixel Transfer
Mode timing. DVLD is asserted every time the output sample
rate converter has a valid output. When DVLD and ACTIVE
are used together the visual portion of the image can be
captured. When DVLD is used alone all valid data during the
Horizontal, Vertical and Reference Burst Timing are
available.
The CLK can be run on a 20MHz - 30MHz clock source.
Data will be output (on average) at the Output Data Rate
shown in Table 3 for a given standard. Data is clocked out
synchronous to CLK and will come in bursts. To smooth out
the data output to a regular rate, a CLK of 2X the average
output data rate can be used.
LINES/FRAME
(NTSC, PAL M)
480 ACTIVE
LINES 1 - 22 NOT ACTIVE
LINES 263 - 284 NOT ACTIVE
240 ACTIVE LINES
240 ACTIVE LINES
(LINES 285 - 524)
(LINES 23-262)
ACTIVE PIXELS
NTSC M, PAL M
TOTAL PIXELS
PER FIELD
PER FIELD
NOT ACTIVE
LINE 525
FIGURE 13. ACTIVE VIDEO REGIONS
858
720
NTSC
FRONT
PORCH
RECTANGULAR (SQUARE)
(780)
(640)
HMP8112A
VERTICAL
BLANKING
NUMBER OF PIXELS
ODD FIELD
EVEN FIELD
4-11
8-Bit Pixel Transfer Mode
For 8-Bit Pixel Transfer Mode the Y[7:0] output bus is used to
transfer all YCbCr data. The data is 4:2:2 subsampled but
will only contain the active video portion of the line. See Fig-
ure 15 for 8-Bit Pixel Transfer Mode timing. In this mode, the
data is clocked out at the CLK rate and only clock frequen-
cies of 24.54MHz, 27MHz and 29.5MHz can be used. In 8-
bit Mode, the data is sequenced on the Y[7:0] bus in Cb, Y,
Cr, Y format. ACTIVE is asserted as soon as the mode is
selected. DVLD when asserted, indicates a valid active pixel
is available. Pixels during the horizontal and vertical blanking
are not available. Only the active portions of the video line
are output.
NTSC Square Pixel
NTSC CCIR 601
PAL B, D, G, H, I, N,
COMB N, CCIR601
PAL M CCIR 601
PAL B, D, G, H, I, N
Square Pixel
PAL M Square Pixel
SYNC AND
STANDARD
864
720
PORCH
BACK
PAL
(944)
(768)
TABLE 3. OUTPUT MODE STANDARDS
LINES 1 - 22 NOT ACTIVE
LINES 311 - 335 NOT ACTIVE
PAL B, D, G, H, I, N, COMB N
12.27MHz
14.74MHz
14.74MHz
13.5MHz
13.5MHz
13.5MHz
OUTPUT
288 ACTIVE LINES
288 ACTIVE LINES
(LINES 336 - 623)
DATA
RATE
(LINES 23 - 310)
ACTIVE PIXELS
TOTAL PIXELS
PER FIELD
PER FIELD
LINES 624-625
NOT ACTIVE
(WITH SYNCS)
780 x 525
858 x 525
864 x 625
858 x 525
944 x 625
780 x 525
PIXELS
TOTAL
LINES/FRAME
576 ACTIVE
(PAL)
640 x 480
720 x 480
720 x 576
720 x 480
768 x 576
640 x 480
ACTIVE
PIXELS