hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 13

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

I
The HMP8112A utilizes an I
gram the internal configuration registers. This standard
mode (up to 100 KBPS) interface consists of the bidirectional
Serial Data Line (SDA) and the Serial Clock Line (SCL). The
implementation on the HMP8112A is a simple slave interface
that will not respond to general calls and cannot initiate a
transfer. The SDA and SCL control pins should be pulled
high through external 4k: pullup resistors to
The I
HMP8112A always uses chip address 0x88. There are 28
internal registers used to program and configure the
decoder. The I
auto-increments through the entire register space and can
be written. The autoincrement pointer will wrap after the last
register has been accessed (Product ID Register) and
should be set to the desired starting address each time an
access is started. For a write transfer, the I
address is the first part of a serial transfer. Then the internal
DATA WRITE
DATA READ
2
C Control Interface
2
SDA
SCL
C clock/data timing is shown below in Figure 16. The
SDA
S
S
SCL
1000 1000 (R/W)
CHIP ADDR
CHIP ADDR
1000 1000
2
C control port contains a pointer register that
0x88
0x88
CONDITION
START
t
S
BUF
A
A
2
C control bus interface to pro-
SUB ADDR
SUB ADDR
ADDRESS
t
LOW
t
SU:DATA
1-7
FIGURE 18. REGISTER WRITE/READ FLOW
t
t
HD:DATA
HIGH
A
A
2
FIGURE 17. I
V
REGISTER
POINTED
TO BY
SUB ADDR
FIGURE 16. I
S
C device base
CC
DATA
R/W
.
CHIP ADDR
8
t
R
0x89
HMP8112A
A
MAY BE REPEATED
OPTIONAL FRAME
2
t
2
C SERIAL DATA FLOW
F
C TIMING DIAGRAM
ACK
4-13
9
DATA
n TIMES
A
register pointer is loaded and a series of registers can be
written. If multiple registers are written, the pointer register
will autoincrement up through the register address space. A
stop cycle is used to end the transfer after the desired num-
ber of registers are programmed.
For a read transfer, the I
the serial transfer. Then the internal register pointer is
loaded. At this point another start cycle is initiated to access
the individual registers. Figure 18 shows the programming
flow for read transfer of the internal registers. Multiple regis-
ters can be read and the pointer register will autoincrement
up through the pointer register address space. On the last
data read, an acknowledge should not be issued. A stop
cycle is used to end the transfer after the desired number of
registers are read.
The HMP8112A contains a product ID register that can be
used to identify the presence of a board during a Plug ’n Play
detection software algorithm. The Product ID Code register is
at sub address 0x1B and always returns a data value of 0x12.
REGISTER
POINTED
TO BY
SUB ADDR
DATA
A
1-7
P
DATA
A
MAY BE REPEATED
OPTIONAL FRAME
DATA
n TIMES
FROM MASTER
FROM HMP8112A
8
2
C device address is the first part of
NA
ACK
P
9
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
CONDITION
STOP
P
t
SU:STOP