hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 20

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

NUMBER
NUMBER
NUMBER
15 - 10
6, 5, 4
7 - 0
9 - 8
BIT
BIT
BIT
7
3
2
1
0
DC RESTORE
END Time (LSB)
Not Used
DC RESTORE
END Time (MSB)
Square Pixel/ITU-R
BT601 Select
Output Field Control
“FLD_CONT(2-0)”
8/16 output Select
OEN
Vertical Pixel Siting
Not Used
FUNCTION
FUNCTION
FUNCTION
This register provides a programmable delay for the internal DC RESTORE signal. This
is the lower byte of the 10-bit word.
Write Ignored, Read 0’s
This register provides a programmable delay for the internal DC RESTORE signal. This
is the upper byte of the 10-bit word.
When “1”, Square pixel output is selected, when “0” ITU-R BT601 output rate is selected.
These bits control the field capture rate of the HMP8112A. The user can select every 4th
field, every other field or every field of video to be output to the data port.
000 = No Capture Enabled
001 = Capture every 4th field
010 = Capture every 2nd field
011 = Capture every 2nd odd field
100 = Capture every 2nd even field
101 = Capture every odd field
110 = Capture every even field
111 = Capture all fields
When “1”, the 8-bit Burst Transfer output mode is selected. When “0”, the 16-bit Synchro-
nous Pixel Transfer output mode is selected.
This bit enables the Y(7-0), CbCr(7-0), ACTIVE, FIELD, HSYNC, VSYNC and DVLD out-
puts. 1 = Outputs enabled; 0 = three-stated.
When this bit is cleared (‘0’) the chrominance pixels have a 1/2 line pixel offset from their
associated luminance pixel in a 4:2:2 subsampled scheme. When this bit is set (‘1’) the
pixel siting is line aligned with the luminance pixels in a 4:2:2 subsampled scheme. The
bit is cleared by a RESET.
Write Ignored, Read 0’s
TABLE 27. DC RESTORE END TIME (MSB) REGISTER
TABLE 26. DC RESTORE END TIME (LSB) REGISTER
TABLE 28. OUTPUT FORMAT CONTROL REGISTER
SUB ADDRESS = 0x14
SUB ADDRESS = 0x15
SUB ADDRESS = 0x16
HMP8112A
4-20
DESCRIPTION
DESCRIPTION
DESCRIPTION
0101 0010
0000 0000
RESET
RESET
RESET
STATE
STATE
STATE
(0x52)
(0x00)
000
0
0
0
0
0
B
B
B
B
B
B
B
B