hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 39

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

PCB Layout Considerations
A PCB board with a minimum of 4 layers is recommended,
with layers 1 and 4 (top and bottom) for signals and layers 2
and 3 for power and ground. The PCB layout should
implement the lowest possible noise on the power and
ground planes by providing excellent decoupling. PCB trace
lengths between groups of V
short as possible.
The optimum layout places the HMP8112A as close as pos-
sible to the power supply connector and the video output
connector.
Component Placement
External components should be positioned as close as pos-
sible to the appropriate pin, ideally such that traces can be
connected point to point. Chip capacitors are recommended
where possible, with radial lead ceramic capacitors the sec-
ond-best choice.
Power supply decoupling should be done using a 0.1PF
ceramic capacitor in parallel with a 0.01PF chip capacitor for
each group of V
tors should be located as close to the power and ground pins
as possible, using short, wide traces.
Digital Ground Plane
All GND pins on the HMP8112A should be connected to the
digital ground plane of the board.
Analog Ground Plane
A separate analog ground plane for the HMP8112A is rec-
ommended. All AGND pins on the HMP8112A should be
connected to the analog ground plane. This analog ground
plane should be connected to the board’s digital ground
plane at a single point.
Analog Power Plane
The HMP8112A should have its own V
isolated from the common power plane of the board, with a
gap between the two power planes of at least 1/8 inch. All
V
analog power plane. The analog power plane should be
connected to the board’s normal V
single point though a low-resistance ferrite bead, such as a
Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK
BF45-4001. The ferrite bead provides resistance to
switching
HMP8112A. A single 47PF capacitor should also be used
between the analog power plane and the ground plane to
control low-frequency power supply ripple.
AA
pins on the HMP8112A must be connected to this
currents,
AA
and V
improving
CC
CC
pins to ground. These capaci-
and GND pins should be as
the
CC
AA
power plane that is
power plane at a
performance
HMP8112A
of
4-39
If a separate linear regulator is used to provide power to the
analog power plane, the power-up sequence should be
designed to ensure latchup will not occur. A separate linear reg-
ulator is recommended if the power supply noise on the V
pins exceeds 200mV.
Analog Signals
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
crosstalk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the ana-
log signals. The analog input traces should also not overlay
the V
ply rejection.
Evaluation Boards
The HMP8156EVAL2 stand-alone evaluation board allows
connecting the NTSC/PAL decoder into an IBM PC ISA slot
for evaluation. The board contains the HMP8112A
NTSC/PAL decoder, 2 Mbytes of VRAM and a encoder. The
board can accept Composite or S-Video input and display
video on a stand composite or S-Video display. The ISA bus
and Windows 95 evaluation software allows easy plug and
play of the decoder for analysis with such tools as a VM700
video test system.
Related Application Notes
Application Notes are also available on the Harris Multimedia
web site at:
AN9644: Composite Video Separation Techniques
AN9716: Widescreen Signalling
AN9717: YCbCr to RGB Considerations
AN9728: BT.656 Video Interface for ICs
AN9738: VMI Video Interface for ICs
AA
http://www.semi.harris.com/datasheets/mmedia.
power plane to maximize high-frequency power sup-
AA