lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet - Page 12

• Manufacturer Part Number: lh28f160s5h-l
• Description: M-bit Smart Flash Memories Fast Programming
• Manufacturer: Sharp Microelectronics of the Americas

NOTES :
1. Bus operations are defined in Table 2.1 and Table 2.2.
2. X = Any valid address within the device.
3. SRD = Data read from status register. See Table 13.1
4. Following the Read Identifier Codes command, read
Read Array/Reset
Read Identifier Codes
Query
Read Status Register
Clear Status Register
Block Erase Setup/Confirm
Full Chip Erase Setup/Confirm
Word/Byte Write Setup/Write
Alternate Word/Byte Write
Setup/Write
Multi Word/Byte Write
Setup/Confirm
Block Erase and (Multi)
Word/Byte Write Suspend
Confirm and Block Erase and
(Multi) Word/Byte Write Resume
Block Lock-Bit Set
Setup/Confirm
Block Lock-Bit Reset
Setup/Confirm
STS Configuration
Level-Mode for Erase
and Write (RY/BY# Mode)
STS Configuration
Pulse-Mode for Erase
STS Configuration
Pulse-Mode for Write
STS Configuration Pulse-Mode
for Erase and Write
IA = Identifier code address : see Fig. 2.
QA = Query offset address.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched
ID = Data read from identifier codes.
QD = Data read from query database.
operations access manufacture, device and block status
codes. See Section 4.2 for read identifier code data.
COMMAND
on the rising edge of WE# or CE# (whichever
goes high first).
for a description of the status register bits.
BUS CYCLES
REQ’D.
≥ 2
≥ 2
≥ 4
1
2
1
2
2
2
2
1
1
2
2
2
2
2
2
Table 3 Command Definitions
NOTE
5, 6
5, 6
4
5
9
5
5
7
8
Oper
- 12 -
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(NOTE 1)
FIRST BUS CYCLE
5. If the block is locked, WP# must be at V
6. Either 40H or 10H is recognized by the WSM as the
7. A block lock-bit can be set while WP# is V
8. WP# must be at V
9. Following the Third Bus Cycle, inputs the write address
10. Commands other than those shown above are reserved
Addr
block erase or (multi) word/byte write operations.
Attempts to issue a block erase or (multi) word/byte write
to a locked block while RP# is V
byte write setup.
block lock-bits operation simultaneously clears all block
lock-bits.
and write data of "N" times. Finally, input the confirm
command "D0H".
by SHARP for future device implementations and should
not be used.
WA
WA
WA
BA
BA
(NOTE 2)
X
X
X
X
X
X
X
X
X
X
X
X
X
(NOTE 10)
Data
FFH
E8H
B0H
D0H
B8H
B8H
B8H
B8H
90H
98H
70H
50H
20H
30H
40H
10H
60H
60H
(NOTE 3)
IH
Oper
to clear block lock-bits. The clear
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
SECOND BUS CYCLE
(NOTE 1)
LH28F160S5-L/S5H-L
IH
Addr
.
WA
WA
WA
QA
BA
BA
IA
(NOTE 2)
X
X
X
X
X
X
X
IH
IH
.
Data
to enable
SRD
D0H
D0H
D0H
N
01H
00H
01H
02H
03H
WD
WD
QD
ID
(NOTE 3)
–
1