lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet - Page 23

• Manufacturer Part Number: lh28f160s5h-l
• Description: M-bit Smart Flash Memories Fast Programming
• Manufacturer: Sharp Microelectronics of the Americas

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
SR.3 = V
SR.2 = WRITE SUSPEND STATUS (WSS)
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Erase or Clear Block Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
1 = V
0 = V
1 = Write Suspended
0 = Write in Progress/Completed
1 = Block Lock-Bit and/or WP# Lock Detected,
0 = Unlock
SMS
7
7
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
(ECBLBS)
(WSBLBS)
Operation Abort
PP
PP
PP
STATUS (VPPS)
Low Detect, Operation Abort
OK
BESS
6
R
6
ECBLBS
Table 13.2 Extended Status Register Definition
5
R
5
Table 13.1 Status Register Definition
WSBLBS
4
R
4
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NOTES :
Check STS or SR.7 to determine block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
completion.
SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (multi) word/byte write, block lock-bit configuration or
STS configuration attempt, an improper command sequence
was entered.
SR.3 does not provide a continuous indication of V
The WSM interrogates and indicates the V
block erase, full chip erase, (multi) word/byte write or block
lock-bit configuration command sequences. SR.3 is not
guaranteed to reports accurate feedback only when V
V
SR.1 does not provide a continuous indication of block lock-bit
values. The WSM interrogates block lock-bit, and WP# only
after block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration command sequences. It informs
the system, depending on the attempted operation, if the block
lock-bit is set and/or WP# is not V
configuration codes after writing the Read Identifier Codes
command indicates block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
NOTES :
After issue a Multi Word/Byte Write command : XSR.7
indicates that a next Multi Word/Byte Write command is
available.
XSR.6-0 are reserved for future use and should be masked
out when polling the extended status register.
PPH1
VPPS
.
3
R
3
WSS
2
R
2
LH28F160S5-L/S5H-L
IH
DPS
. Reading the block lock
1
R
1
PP
level only after
PP
0
0
R
R
level.
PP
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