lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet - Page 18

• Manufacturer Part Number: lh28f160s5h-l
• Description: M-bit Smart Flash Memories Fast Programming
• Manufacturer: Sharp Microelectronics of the Americas

4.6 Block Erase Command
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by a block erase
confirm.
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence
is written, the device automatically outputs status
register data when read (see Fig. 3). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit
SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V
V
high voltage, block contents are protected against
erasure. If block erase is attempted while V
V
block erase requires that the corresponding block
lock-bit be cleared or if set, that WP# = V
erase is attempted when the corresponding block
lock-bit is set and WP# = V
be set to "1".
PPLK
CC1/2
, SR.3 and SR.5 will be set to "1". Successful
and V
This
PP
= V
command
PPH1
. In the absence of this
IL
, SR.1 and SR.5 will
sequence
IH
. If block
requires
PP
CC =
≤
- 18 -
4.7 Full Chip Erase Command
This command followed by a confirm command
(D0H) erases all of the unlocked blocks. A full chip
erase setup is first written, followed by a full chip
erase confirm. After a confirm command is written,
device erases the all unlocked blocks from block 0
to block 31 block by block. This command
sequence requires appropriate sequencing. Block
preconditioning, erase and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle full chip erase sequence is
written, the device automatically outputs status
register data when read (see Fig. 4). The CPU can
detect full chip erase completion by analyzing the
output data of the STS pin or status register bit
SR.7.
When the full chip erase is complete, status register
bit SR.5 should be checked. If erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued. If error is detected on a
block during full chip erase operation, WSM stops
erasing. Reading the block valid status by issuing
Read ID Codes command or Query command
informs which blocks failed to its erase.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Full Chip
Erase command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable full chip erasure can only occur when V
V
voltage, block contents are protected against
erasure. If full chip erase is attempted while V
V
WP# = V
block lock-bits status. When WP# = V
unlocked blocks are erased. In this case, SR.1 and
SR.4 will not be set to "1". Full chip erase can not
be suspended.
CC1/2
PPLK
, SR.3 and SR.5 will be set to "1". When
and V
IH
, all blocks are erased independent of
PP =
V
PPH1
. In the absence of this high
LH28F160S5-L/S5H-L
IL
, only
PP
CC =
≤