lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet - Page 5

• Manufacturer Part Number: lh28f160s5h-l
• Description: M-bit Smart Flash Memories Fast Programming
• Manufacturer: Sharp Microelectronics of the Americas

PIN DESCRIPTION
CE
DQ
SYMBOL
BYTE#
A
0
WE#
WP#
GND
STS
RP#
OE#
0
V
#, CE
V
0
NC
-DQ
-A
PP
CC
20
15
1
#
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
DRAIN
INPUT
INPUT
INPUT
INPUT
INPUT
OPEN
INPUT
INPUT
TYPE
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
A
A
A
A
DATA INPUT/OUTPUTS :
DQ
memory array, status register, query, and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
DQ
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode (BYTE# = V
CHIP ENABLE : Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE
consumption to standby levels. Both CE
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP# V
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE : Gates the device’s outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#) : Indicates the status of the internal WSM. When configured in level
mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an
internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of
the STATUS pin, see the Configuration command (Table 3 and Section 4.14).
WRITE PROTECT : Master control for block locking. When V
be erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE : BYTE# V
on DQ
A
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes or
configuring block lock-bits. With V
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an
invalid V
and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation.
Do not float any power pins. With V
are inhibited. Device operations at invalid V
CHARACTERISTICS") produce spurious results and should not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
0 :
1
5
16
0
-A
-A
input buffer.
-A
8
0
Byte Select Address. Not used in x16 mode (can be floated).
-DQ
-DQ
4 :
15 :
20
0-7
Column Address. Selects 1 of 16-bit lines.
Row Address. Selects 1 of 2 048-word lines.
: Block Address.
15 :
7 :
PP
, and DQ
Inputs data and commands during CUI write cycles; outputs data during
Inputs data during CUI write cycles in x16 mode; outputs data during memory
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results
8-15
float. BYTE# V
0
# or CE
- 5 -
IL
IH
places device in x8 mode. All data are then input or output
enables normal operation. When driven V
NAME AND FUNCTION
1
PP
# V
IL
≤ V
CC
IH
). Data is internally latched during a write cycle.
IH
places the device in x16 mode, and turns off the
0
PPLK
≤ V
# and CE
deselects the device and reduces power
LKO
, memory contents cannot be altered. Block
, all write attempts to the flash memory
CC
1
# must be V
voltage (see Section 6.2.3 "DC
LH28F160S5-L/S5H-L
IL
IL
, locked blocks can not
to select the devices.
IL
, RP# inhibits