lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet - Page 6

• Manufacturer Part Number: lh28f160s5h-l
• Description: M-bit Smart Flash Memories Fast Programming
• Manufacturer: Sharp Microelectronics of the Americas

1 INTRODUCTION
This datasheet contains LH28F160S5-L/S5H-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160S5-L/
S5H-L flash memories documentation also includes
ordering information which is referenced in
Section 7.
1.1 Product Overview
The LH28F160S5-L/S5H-L are high-performance
16 M-bit Smart 5 flash memories organized as
2 MB x 8/1 MB x 16. The 2 MB of data is arranged
in thirty-two 64 k-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Fig.1.
Smart 5 technology provides a choice of V
V
system performance and power expectations. V
at 5 V eliminates the need for a separate 12 V
converter, while V
write performance. In addition to flexible erase and
program voltages, the dedicated V
complete data protection when V
Internal V
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, full chip erase, (multi)
PP
Table 1 V
combination, as shown in Table 1, to meet
V
CC
VOLTAGE
CC
5 V
Offered by Smart 5 Technology
CC
and V
and V
PP
PP
= 5 V maximizes erase and
PP
detection circuitry auto-
Voltage Combination
V
PP
PP
VOLTAGE
≤ V
5 V
PP
PPLK
pin gives
.
CC
and
PP
- 6 -
word/byte write and block lock-bit configuration
operations.
A block erase operation erases one of the device’s
64 k-byte blocks typically within 0.34 second (5 V
V
block can be independently erased 100 000 times
(3.2 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
A word/byte write is performed in byte increments
typically within 9.24 µs (5 V V
word/byte write has high speed write performance
of 2 µs/byte (5 V V
write suspend mode enables the system to read
data from, or write data to any other flash memory
array location.
Individual block locking uses a combination of bits
and WP#, thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or
block lock-bit configuration operation is finished.
The STS output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using STS
minimizes both CPU overhead and system power
consumption. STS pin can be configured to
different states using the Configuration command.
The STS pin defaults to RY/BY# operation. When
low, STS indicates that the WSM is performing a
CC
, 5 V V
PP
) independent of other blocks. Each
CC
, 5 V V
LH28F160S5-L/S5H-L
PP
CC
). (Multi) word/byte
, 5 V V
PP
). A multi