tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 48

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3
Reset Circuit
2.3.2
2.3.3
2.3.4
Instruction
execution
RESET output
Internal reset
signal
Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Note 3: Varies on account of external condition: voltage or capacitance
tion from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap re-
set will be generated. The reset time is maximum 24/fc[s] (1.5μs at 16.0 MHz). Then, the RESET pin out-
puts "L" level during maximum 24/fc[s].
the CPU. (The oscillation is continued without stopping.)
imum 24/fc[s] (1.5μs at 16.0MHz).
Address trap reset
Watchdog timer reset
System clock reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruc-
Refer to Section “Watchdog Timer”.
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of
The reset time is maximum 24/fc (1.5 μs at 16.0 MHz). Then, the RESET pin outputs "L" level during max-
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area
-
-
-
is alternative.
In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
JP a
Address trap is occurred
Figure 2-16 Address Trap Reset
Maximum 24/fc [s]
("L" output)
Note 3
Page 30
4/fc to 12/fc [s]
Reset release
16/fc [s]
TMP86FH46BNG
Instruction at address r