tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 57

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.5
3.6
3.7
3.8
3.5.1
3.5.2
(INTSW is highest prioritized interrupt).
erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable in-
terrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is reques-
ted.
dress trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contempo-
rary process is broken and INTATRAP interrupt process starts, soon after it is requested.
cuits (Pulse inputs of less than a certain time are eliminated as noise).
terrupt input pin or an input/output port, and is configured as an input port during reset.
control register (EINTCR).
Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing
Use the SWI instruction only for detection of the address error or for debugging.
Undefined Instruction Interrupt (INTUNDEF)
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen-
Address Trap Interrupt (INTATRAP)
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or ad-
External Interrupts
The TMP86FH46BNG has 6 external interrupt inputs. These inputs are equipped with digital noise reject cir-
Edge selection is also possible with INT1 to INT4. The INT0/P00 pin can be configured as either an external in-
Edge selection, noise reject control and INT0/P00 pin function selection are performed by the external interrupt
Note:The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software inter-
Note:The operating mode under address trapped, whether to be reset output or interrupt processing, is selected
ory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated
and an address error is detected. The address error detection range can be further expanded by writing FFH
to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched
from RAM, DBR or SFR areas.
dress.
Address error detection
Debugging
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return in-
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt serv-
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent mem-
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting ad-
rupt (SWI) does.
on watchdog timer control register (WDTCR).
terrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Exam-
ple 2).
ice task is performed but not the main task.
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TMP86FH46BNG