tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 54

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.4
Interrupt Sequence
3.4.2
Note 1: a: Return address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
PC
SP
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
service program
the level of current servicing interrupt is requested.
case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
iced, before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with
length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would
simply nested.
cludes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are
saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid us-
ing the same data memory area for saving registers. The following methods are used to save/restore the general-
purpose registers.
1-machine cycle
Saving/restoring general-purpose registers
first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serv-
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, in-
a − 1
instruction
Execute
a
FFF2H
FFF3H
a + 1
Vector table address
Figure 3-2 Vector table address,Entry address
n
D2H
03H
Interrupt acceptance
a
n − 1
Vector
n − 2
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b
b + 1
b + 2
instruction
Execute
b + 3
n - 3
D203H
D204H
c + 1
Entry address
Interrupt service task
0FH
06H
n − 2 n − 1
c + 2
Execute RETI instruction
Interrupt
service
program
TMP86FH46BNG
a
a + 1
n
a + 2