tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 74

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.3
Address Trap
6.3
Watchdog Timer Control Register 1
6.3.1
6.3.2
6.3.3
Watchdog Timer Control Register 2
WDTCR1
(0034H)
WDTCR2
(0035H)
dress traps.
Address Trap
The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate ad-
cute an instruction in the internal RAM area, clear WDTCR1<ATAS> to “0”. To enable the
WDTCR1<ATAS> setting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
the setting in WDTCR1<ATAS>.
WDTCR1<ATOUT>.
tempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
ter flag (IMF).
ready accepted, the new address trap is processed immediately and the previous interrupt is held pending. There-
fore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
Selection of Address Trap in Internal RAM (ATAS)
Selection of Operation at Address Trap (ATOUT)
Address Trap Interrupt (INTATRAP)
WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To exe-
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of
When an address trap is generated, either the interrupt request or the reset request can be selected by
While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an at-
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas-
When an address trap interrupt is generated while the other interrupt including an address trap interrupt is al-
To generate address trap interrupts, set the stack pointer beforehand.
ATOUT
WDTCR2
7
ATAS
7
6
Select address trap generation
in the internal RAM area
Select operation at address trap
6
Write
Watchdog timer control code
and address trap area control
code
ATAS
5
5
ATOUT
4
4
(WDTEN)
3
0: Generate no address trap
1: Generate address traps (After setting ATAS to “1”, writing the control code
D2H to WDTCR2 is required)
0: Interrupt request
1: Reset request
D2H: Enable address trap area selection (ATRAP control code)
4EH: Clear the watchdog timer binary counter (WDT clear code)
B1H: Disable the watchdog timer (WDT disable code)
Others: Invalid
3
Page 56
2
2
(WDTT)
1
1
(WDTOUT)
0
0
(Initial value: **** ****)
(Initial value: **11 1001)
TMP86FH46BNG
Write
Write
only
only