tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 95

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example :Generating a pulse which is high-going for 800 μs and low-going for 200 μs
8.3.6
(fc = 16 MHz)
formed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input pulse
to the TC1 pin or the command start. TC1CR<MPPG1> specifies whether a duty pulse is produced continuous-
ly or not (one-shot pulse).
ative pulse can be generated. Since the inverted level of the timer F/F1 output level is output to the PPG pin,
specify TC1CR<TFF1> to “0” to set the high level to the PPG pin, and “1” to set the low level to the PPG
pin. Upon reset, the timer F/F1 is initialized to “0”.
Programmable Pulse Generate (PPG) Output Mode
Note 1: To change TC1DRA or TC1DRB during a run of the timer, set a value sufficiently larger than the count val-
Note 2: Do not change TC1CR<TFF1> during a run of the timer. TC1CR<TFF1> can be set correctly only at initi-
Note 3: In the PPG mode, the following relationship must be satisfied.
Note 4: Set TC1DRB after changing the mode of TC1M to the PPG mode.
In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per-
Since the output level of the PPG pin can be set with TC1CR<TFF1> when the timer starts, a positive or neg-
・ When TC1CR<MPPG1> is set to “0” (Continuous pulse generation)
・ When TC1CR<MPPG1> is set to “1” (One-shot pulse generation)
the level of the PPG pin is inverted and an INTTC1 interrupt request is generated. The up-counter con-
tinues counting. When a match between the up-counter and the TC1DRA value is detected, the lev-
el of the PPG pin is inverted and an INTTC1 interrupt request is generated. The up-counter is
cleared at this time, and then continues counting and pulse generation.
fore the counter stops.
the level of the PPG pin is inverted and an INTTC1 interrupt request is generated. The up-counter con-
tinues counting. When a match between the up-counter and the TC1DRA value is detected, the lev-
el of the PPG pin is inverted and an INTTC1 interrupt request is generated. TC1CR<TC1S> is
cleared to “00” automatically at this time, and the timer stops. The pulse generated by PPG retains
the same level as that when the timer stops.
ue of the counter. Setting a value smaller than the count value of the counter during a run of the timer
may generate a pulse different from that specified.
alization (after reset). When the timer stops during PPG, TC1CR<TFF1> can not be set correctly from
this point onward if the PPG output has the level which is inverted of the level when the timer starts. (Set-
ting TC1CR<TFF1> specifies the timer F/F1 to the level inverted of the programmed value.) Therefore,
the timer F/F1 needs to be initialized to ensure an arbitrary level of the PPG output. To initialize the tim-
er F/F1, change TC1CR<TC1M> to the timer mode (it is not required to start the timer mode), and then
set the PPG mode. Set TC1CR<TFF1> at this time.
TC1DRA > TC1DRB
When a match between the up-counter and the TC1DRB value is detected after the timer starts,
When TC1S is cleared to “00” during PPG output, the PPG pin retains the level immediately be-
When a match between the up-counter and the TC1DRB value is detected after the timer starts,
LD
LDW
LDW
LD
Setting port
(TC1CR), 10000111B
(TC1DRA), 007DH
(TC1DRB), 0019H
(TC1CR), 10010111B
Page 77
; Sets the PPG mode, selects the source clock
; Sets the cycle (1 ms ÷ 2
; Sets the low-level pulse width (200 μs ÷ 2
; Starts the timer
7
/fc μs = 007DH)
7
/fc = 0019H)
TMP86FH46BNG