tmp86fh09amg TOSHIBA Semiconductor CORPORATION, tmp86fh09amg Datasheet - Page 23

• Manufacturer Part Number: tmp86fh09amg
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.2.3.3
The internal status immediately prior to the halt is held with a lowest power consumption during STOP
mode.
ting (Either level-sensitive or edge-sensitive can be programmable selected) to the STOP pin. After the
warm-up period is completed, the execution resumes with the instruction which follows the STOP mode
start instruction.
(4)
(5)
(6)
(7)
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a input-
STOP mode
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stop-
ped; output from the 1st to 6th stages is also stopped.
ted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the
low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, ex-
cept that operation returns to NORMAL2 mode.
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; howev-
er, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releas-
ing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1
mode. In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; out-
put from the 1st to 6th stages is also stopped.
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-
frequency clock.
mode is enabled by setting “1” on bit SYSCR2<TGHALT>.
the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selec-
ted with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When
IMF = “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, inter-
rupt processing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the
INTTBT interrupt latch is set after returning to SLOW1 mode.
Switching back and forth between SLOW1 and SLOW2 modes are performed by
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are hal-
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
IDLE2 mode
SLEEP1 mode
SLEEP2 mode
SLEEP0 mode
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TMP86FH09AMG