tmp86fh09amg TOSHIBA Semiconductor CORPORATION, tmp86fh09amg Datasheet - Page 25

• Manufacturer Part Number: tmp86fh09amg
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

System Control Register 1
System Control Register 2
SYSCR1
SYSCR2
(0038H)
(0039H)
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transit-
Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 0 and 1 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause exter-
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: In case of setting as STOP mode is released by a rising edge of STOP pin input, the release setting by STOP5 to
Note 8: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 be-
Note 9: The warming-up time should be set correctly for using oscillator.
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is
Note 2: *: Don’t care, TG: Timing generator
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the pe-
STOP
TGHALT
XEN
SYSCK
OUTEN
ing from SLOW mode to STOP mode.
nal interrupt request on account of falling edge.
STOP2 on STOPCR register is prohibited.
comes High-Z mode.
cleared to “0” when SYSCK = “1”.
riod of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
XTEN
RETM
STOP
RELM
IDLE
XEN
7
WUT
7
RELM
XTEN
High-frequency oscillator control
Low-frequency oscillator control
Main system clock select (Write)/
main system clock monitor
(Read)
CPU and watchdog timer con-
trol (IDLE1/2 and SLEEP1/2
modes)
TG control (IDLE0 and SLEEP0
modes)
6
6
STOP mode start
Release method for STOP
mode
Operating mode after STOP
mode
Port output during STOP mode
Warm-up time at releasing
STOP mode
SYSCK
RETM
5
5
OUTEN
IDLE
4
4
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
0: Edge-sensitive release
1: Level-sensitive release
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
0: High impedance
1: Output kept
0: Turn off oscillation
1: Turn on oscillation
0: Turn off oscillation
1: Turn on oscillation
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2
modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)
3
3
00
01
10
11
WUT
Page 15
TGHALT
2
2
Return to NORMAL mode
3 x 2
3 x 2
1
1
2
2
16
14
/fc
/fc
16
14
/fc
/fc
0
0
(Initial value: 0000 00**)
(Initial value: 1000 *0**)
Return to SLOW mode
3 x 2
3 x 2
TMP86FH09AMG
2
2
13
6
/fs
/fs
13
6
/fs
/fs
R/W
R/W
R/W
R/W
R/W
R/W
R/W