se97pw/1 NXP Semiconductors, se97pw/1 Datasheet - Page 21

• Manufacturer Part Number: se97pw/1
• Description: Se97 Memory Module Temp Sensor With Integrated Spd
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SE97_2
Product data sheet
Table 11.
Bit
7
6
5
4
3
2
1
0
Symbol
CTLB
AWLB
CEVNT
ESTAT
EOCTL
CVO
EP
EMD
Configuration Register (address 01h) bit description
Description
Critical Trip Lock bit.
This bit is initially cleared. When set, this bit will return a ‘1’, and remains
locked until cleared by internal Power-on reset. This bit can be written with a
single write and do not require double writes.
Alarm Window Lock bit.
This bit is initially cleared. When set, this bit will return a ‘1’ and remains
locked until cleared by internal power-on reset. This bit can be written with a
single write and does not require double writes.
Clear EVENT (write only).
When read, this register always returns zero.
EVENT Status (read only).
The actual event causing the event can be determined from the Read
Temperature Register. Interrupt Events can be cleared by writing to the
‘Clear EVENT’ bit (CEVNT). Writing to this bit will have no effect.
EVENT Output Control.
When either of the lock bits is set, this bit cannot be altered until unlocked.
Critical Event Only.
When the alarm window lock bit is set, this bit cannot be altered until
unlocked.
EVENT Polarity.
EVENT Mode.
When either of the alarm or critical lock bits is set, this bit cannot be altered
until unlocked.
0 — Critical Alarm Trip Register is not locked and can be altered (default)
1 — Critical Alarm Trip Register settings cannot be altered
0 — Upper and Lower Alarm Trip Registers are not locked and can be
altered (default)
1 — Upper and Lower Alarm Trip Registers setting cannot be altered
0 — no effect (default)
1 — clears active EVENT in Interrupt mode. Writing to this register has no
effect in Comparator mode.
0 — EVENT output condition is not being asserted by this device (default)
1 — EVENT output pin is being asserted by this device due to Alarm
Window or Critical Trip condition
0 — EVENT output disabled (default)
1 — EVENT output enabled
0 — EVENT output on Alarm or Critical temperature event (default)
1 — EVENT only if temperature is above the value in the critical
temperature register
0 — active LOW (default)
1 — active HIGH. When either of the alarm or critical lock bits is set, this
bit cannot be altered until unlocked.
0 — comparator output mode (default)
1 — interrupt mode
Rev. 02 — 12 October 2007
Memory module temp sensor with integrated SPD
…continued
© NXP B.V. 2007. All rights reserved.
SE97
21 of 43