w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 35

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

TABLE 7.6 Multiframe structure in S/T interface
Frame Number
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-
-
-
-
-
Multiframe synchronization: Synchronization is achived when the M bit pattern has been correctly received during
20 consecutive frames starting from frame number 1.
Note: Criterion for multiframe synchronization is not defined in I.430 Recommendation.
S bits receive and detect: When synchronization is achieved, the four received S bits in frames 1,6,11,16 are stored
as S1 to S4 in the SQR register respectively. A change in the recived four bits (S1-4) is indicated by an interrupt
(ISC in D_EXIR register and SCC in CIR register).
Multiframe synchronization monitoring: Multiframe synchronization is constantly monitored. The synchronization
state is indicated by the MSYN bit in the SQR register.
Q bits transmit and F
SQXR register are transmitted as the four Q bits (F
transmitted is a mirror of the received F
bit.
The multiframe synchronization can be disabled by setting MFD bit in the D_MODE register.
According to I.430 Recommendation, the S/Q channel can be used as operation and maintenance signalling
channel. At transmitter, a S/Q code for a message shall be repeated at least six times or as many as necessary to
obtain the desired response. At receiver, a message shall be considered received only when the proper codes is
received three consecutive times.
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
F
A
NT-to-TE
-bit position
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ONE
ONE
ONE
ONE
A
mirroring: When multiframe synchronization is achived, the four bits Q1-4 stored in the
NT-to-TE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
M bit
ONE
A
-bit. At loss of synchronization, the mirroring is resumed at the next F
A
NT-to-TE
-bit position) in frames 1,6,11 and 16. Otherwise the F
-35 -
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S bit
S1
S2
S3
S4
F
A
TE-to-NT
-bit position
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
W6692 PCI ISDN S/T-Controller
Q1
Q2
Q3
Q4
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9
A
bit
A
-