w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 42

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

the microprocessor reads out 64 bytes of data from the FIFO. The D_RME interrupt indicates the last segment of a message or a
message with length
register.
are 000000B.
control field and information field.
Receive Message Acknowledgement command (D_CMDR: RACK bit) to explicitly acknowledge the interrupt. The
microprocessor must handle the interrupt before more than 64 bytes of data are received. This corresponds to a maximum
microprocessor reaction time of 32 ms at 16 kbps data rate.
and status bit.
7.6.3 Transmission of Frames in D Channel
the micro-processor can write up to 64 bytes of data into the FIFO and use the XMS command bit to start frame transmission.
The HDLC transmitter sends the opening flag first and then sends the data in the transmit FIFO.
another block of data. The microprocessor can then write further data to the transmit FIFO and enables the subsequent
transmission by issuing an XMS command.
XMS command bits to finish the frame transmission. The transmitter then transmits the data in the FIFO and appends CRC and
closing flag.
The W6692 will automatically reset the transmitter and send inter frame time fill pattern (all 1's) on D channel. The
microprocessor is informed about this condition via an XDUN (Transmit Data Underrun) interrupt in D_EXIR register. The
microprocessor must wait until transmit FIFO ready (via XFR interrupt ), re-write data, and issue XMS command to re-transmit
the data.
resets the transmitter and causes a transmit FIFO ready condition.
When a D_RMR or D_RME interrupt is generated, the micro-processor must read out the data from D_RFIFO and issues the
If the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt
It is possible to abort a frame by issuing a D_CMDR:XRST (D channel Transmitter Reset) command. The XRST command
If the length of the last segment of message is 64, only D_RME interrupt is generated and the RBC5-0 bits in D_RBCL register
The data between the opening flag and the CRC field are stored in D_RFIFO. For LAPD frame, this includes the address field,
A 128-byte FIFO is provided in the transmit direction. If the transmit FIFO is ready (which is indicated by a D_XFR interrupt),
The microprocessor must write the address, control and information field of a frame into the transmit FIFO.
Every time no more than 64 bytes of data are left in the transmit FIFO, the transmitter generates a D_XFR interrupt to request
If the data written to the FIFO is the last segment of a frame, the microprocessor issues the XME (Transmit Message End) and
If the microprocessor fails to respond the D_XFR interrupt within a given time (32 ms), a data underrun condition will occur.
64 bytes has been received. The length of data is less than or equal to 64 and is specified in the D_RBCL
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W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9